DEMO MANUAL DC1748A
LTM2883 SPI/Digital or
I
2
C µModule Isolator with Adjustable ±12.5V
and 5V Regulated Power
DESCRIPTION
Demonstration circuit 1748A is a serial peripheral interface
bus (SPI) or inter-IC bus (I
2
C) SPI/digital or I
2
C μModule
isolator with adjustable ±12.5V and 5V regulated power
featuring the LTM2883. The demo circuit features an EMI
optimized circuit configuration and printed circuit board
layout. All components are integrated into the μModule
isolator. The demo circuit operates from a single external
supply on V
CC
. The part generates output voltages on V
CC2
,
V
+
, and V
–
, which may be adjusted by external program-
ming resistors. It communicates all necessary signaling
across the isolation barrier through LTC’s isolator μModule
technology.
Design files for this circuit board are available at
http://www.linear.com/demo
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
PERFORMANCE SUMMARY
SYMBOL
V
CC
V
CC2
PARAMETER
Input Supply Range
Regulated Output Voltage
Adjustable Output Voltage Range
Maximum Load Current
V
+
Regulated Output Voltage
Adjustable Output Voltage Range
Maximum Load Current
V
–
Regulated Output Voltage
Adjustable Output Voltage Range
Maximum Load Current
f
MAX
Maximum Data Rate
(T
A
= 25°C)
MIN
4.5
3.0
4.75
3.0
20
12
1.22
20
–12
–1.22
15
–12.5
–13
14
12.5
13
14
TYP
5
3
5
MAX
5.5
3.6
5.25
5.5
UNITS
V
V
V
V
mA
V
V
mA
V
V
mA
MHz
MHz
MHz
kHz
V
DC
V
RMS
kV/μs
CONDITIONS
LTM2883-5
LTM2883-3
DI1
→
O1, Ix
→
DOx, C
L
= 10pF
LTM2883-S, Bidirectional Communication
LTM2883-S, Unidirectional Communication
LTM2883-I
10
4
8
400
560
400
30
V
IORM
Maximum Working Insulation Voltage
Common Mode Transient Immunity
GND to GND2
dc1748af
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DEMO MANUAL DC1748A
OPERATING PRINCIPLES
The LTM2883 contains an isolated DC/DC conversion
system, including a boost converter and inverting charge
pump, with multiple LDO’s to deliver power to the three
output voltage rails from V
CC
. Isolation is maintained by
the separation of GND and GND2 where significant operat-
ing voltages and transients can exist without affecting the
operation of the LTM2883. The logic side ON pin enables
or shuts down the LTM2883. All logic side signals are
referenced to the logic supply pin V
L
. The LTM2883 is
available in two data bus configurations, SPI (-S) or I
2
C
(-I), and with two input voltage ranges, 3.0 to 3.6 volts
(-3) or 4.5 to 5.5 volts (-5).
SPI signaling is controlled by the logic inputs
CS,
SDI,
and SCK.
SDOE
controls the SDO output and is normally
connected to
CS.
The corresponding Isolated side output
signals are
CS2,
SDI2, and SCK2. SDO2 is the isolated
side SPI data input. All of the SPI communication channels
may be used as generic digital I/O.
I
2
C signaling is controlled by the logic inputs SDA and
SCL, corresponding to SDA2 and SCL2 on the isolated
side. The SCL channel is unidirectional supporting master
mode only I
2
C communication. SCL2 output is standard
CMOS push-pull drive. SDA signaling is bidirectional,
and includes an internal current source pull-up on SDA2
supporting up to 200pF of load capacitance.
Demo circuit 1748A is available in four configurations
supporting all versions of the LTM2883. Table 2 details
the demo circuit configurations.
Table 2.
DEMO CIRCUIT
DC1748A-A
DC1748A-B
DC1748A-C
DC1748A-D
INPUT VOLTAGE
3.0V to 3.6V
4.5V to 5.5V
3.0V to 3.6V
4.5V to 5.5V
COMMUNICATION
SPI/Digital
SPI/Digital
I
2
C
I
2
C
The demo circuit has been designed and optimized for low
RF emissions. To this end some features of the LTM2883
are not available for evaluation on the demo circuit. The
logic supply voltage V
L
is tied to V
CC
on the demo circuit,
and the ON pin is not available on the input pin header,
but may be controlled by jumper JP1. EMI mitigation
techniques used include the following.
1. Four layer PCB, allowing for isolated side to logic side
bridge capacitor. The bridge capacitor is formed be-
tween an inner layer of floating copper which overlaps
the logic side and isolated side ground planes. This
structure creates two series capacitors, each with
approximately .008" of insulation, supporting the full
dielectric withstand rating of 2500V
RMS
. The bridge
capacitor provides a low impedance return path for
injected currents due to parasitic capacitances of the
LTM2883’s signal and power isolating elements.
2. Discrete bridge capacitors (C3, C4) mounted between
GND2 and GND. The discrete capacitors provide ad-
ditional attenuation at frequencies below 400MHz.
Capacitors are safety rated type Y2, manufactured by
Murata, part number GA342QR7GF471KW01L.
3. Board/ground plane size has been minimized. This
reduces the dipole antenna formed between the logic
side and isolated side ground planes.
4. Top signal routing and ground floods have been opti-
mized to reduce signal loops, minimizing differential
mode radiation.
5. Common mode filtering is integrated into the input and
output pin headers. Filtering helps to reduce emissions
caused by conducted noise and minimizes the effects
of cabling to common mode emissions.
6. A combination of low ESL and high ESR decoupling is
used. A low ESL ceramic capacitor is located close to
the module minimizing high frequency noise conduction.
A high ESR tantalum capacitor is included to minimize
board resonances and prevent voltage spikes due to
hot plugging of the supply voltage.
dc1748af
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DEMO MANUAL DC1748A
OPERATING PRINCIPLES
EMI performance is shown in Figure 1, measured using
a Gigahertz Transverse Electromagnetic (GTEM) cell and
method detailed in IEC 61000-4-20, “Testing and Mea-
surement Techniques – Emission and Immunity Testing
in Transverse Electromagnetic Waveguides”.
The demo circuit includes provisions for programming
the three output voltage rails. Resistors R5, R6, and R7
allow the V
+
, V
–
, and V
CC2
power rails, respectively, to
be reduced from their nominal operating voltages. The
formulas presented in Table 3 allow selection of the ap-
propriate resistor values.
60
50
40
30
dBμV/m
20
10
0
–10
–20
–30
DC1748A-A
DETECTOR = QuasiPeak
RBW = 120kHz
VBW = 300kHz
SWEEP TIME = 17s
# OF POINTS = 501
0 100 200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
DC1748A F01
Table 3.
VOLTAGE RAIL
V
+
V
–
V
CC2
RESISTOR TO REDUCE OUTPUT
R5 = 150k • (V
+
– 1.22)/(12.5 – V
+
)
R6 = 150k • (1.22 + V
–
)/(–12.5 – V
–
)
R7 = 110k • (V
CC2
– 0.6)/(5 – V
CC2
)
CISPR 22 CLASS B LIMIT
DC1748A-B
Figure 1. DC1748 Radiated Emissions
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DEMO MANUAL DC1748A
QUICK START PROCEDURE
Demonstration circuit 1748A is easy to set up and evalu-
ate the performance of the LTM2883. Refer to Figure 2
for proper measurement equipment setup and follow the
procedure below.
NOTE: When measuring the input or output voltage ripple
or high speed signals, care must be taken to avoid a long
ground lead on the oscilloscope probe.
1. Install JP1 in the ON (default) position.
2. With power off, connect the input power supply to V
CC
and GND on pin header J1.
3. Turn on the power at the input.
NOTE: Make sure that the input voltage does not
exceed 6V.
4. Check for the proper output voltages. V
CC2
= 5V,
V
+
= 12.5V, and V
–
= –12.5V on pin header J2.
5. Once the proper output voltages are established, con-
nect signals to J1 and J2 pin headers as appropriate.
The header pin names and locations are detailed on the
demo board silkscreen below the pin headers.
Figure 2. Demo Board Setup
dc1748af
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