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R
Spartan-II 2.5V FPGA
Automotive IQ Product Family:
Introduction and Ordering
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DS105-1 (v1.4) October 18, 2004
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Product Specification
Introduction
The Spartan™-II 2.5V Field-Programmable Gate Array
(FPGA) Automotive IQ product family gives users high per-
formance, abundant logic resources, and a rich feature set.
The six-member family offers densities ranging from 15,000
to 200,000 system gates, as shown in
Table 1.
Spartan-II devices deliver more gates, I/Os, and features
per Dollar/Euro than other FPGAs by combining advanced
0.18
µm
process technology with a streamlined Vir-
tex™-based architecture. Features include block RAM (to
56K bits), distributed RAM (to 75,264 bits), 16 selectable
I/O standards, and four DLLs. Fast, predictable intercon-
nect means that successive design iterations continue to
meet timing requirements.
The Spartan-II family is a superior alternative to mask-pro-
grammed ASICs. The FPGA avoids the initial cost, lengthy
development cycles, and inherent risk of conventional
ASICs. Also, FPGA programmability permits design
upgrades in the field with no hardware replacement neces-
sary (impossible with ASICs).
•
System level features
- SelectRAM+™ hierarchical memory:
·
16 bits/LUT distributed RAM
·
Configurable 4K-bit block RAM
·
Fast interfaces to external RAM
- Fully PCI compliant
- Low-power segmented routing architecture
- Full readback ability for verification/observability
- Dedicated carry logic for high-speed arithmetic
- Dedicated multiplier support
- Cascade chain for wide-input functions
- Abundant registers/latches with enable, set, reset
- Four dedicated DLLs for advanced clock control
- Four primary low-skew global clock distribution
nets
- IEEE 1149.1 compatible boundary scan logic
Versatile I/O and packaging
- Family footprint compatibility in common packages
- 16 high-performance interface standards
- Zero hold time simplifies system timing
Fully supported by powerful Xilinx development system
- Foundation™ ISE Series: Fully integrated software
- Alliance Series™: For use with third-party tools
- Fully automatic mapping, placement, and routing
Refer to Spartan-II 2.5V FPGA Detailed Functional
Description (DS001-2) for device functional description
Other than the DC parameters listed, all other DC
specifications are the same as referenced in the
Spartan-II 2.5V FPGA DC and Switching
Characteristics (DS001-3) data sheet
Refer to Spartan-II 2.5V FPGA Pinout Tables
(DS001-4) for all pin descriptions
Maximum
Available
User I/O
(1)
86
132
176
176
176
284
Total
Distributed RAM
Bits
6,144
13,824
24,576
38,400
55,296
75,264
Total
Block RAM
Bits
16K
24K
32K
40K
48K
56K
•
Features
•
•
Guaranteed to meet full electrical specifications over
T
J
= –40°C to +125°C
Second generation ASIC replacement technology
- Densities as high as 5,292 logic cells with up to
200,000 system gates
- Streamlined features based on Virtex architecture
- Unlimited reprogrammability
•
•
•
•
Table 1:
Spartan-II FPGA Family Members
Logic
Cells
432
972
1,728
2,700
3,888
5,292
System Gates
(Logic and RAM)
15,000
30,000
50,000
100,000
150,000
200,000
CLB
Array
(R x C)
8 x 12
12 x 18
16 x 24
20 x 30
24 x 36
28 x 42
Total
CLBs
96
216
384
600
864
1,176
Device
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
Notes:
1. All user I/O counts do not include the four global clock/user input pins. See details in
Table 3, page 3.
© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS105-1 (v1.4) October 18, 2004
Product Specification
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Spartan-II 2.5V FPGA Automotive IQ Product Family: Introduction and Ordering Information
R
DC Specifications
Absolute Maximum Ratings
(1)
Symbol
V
CCINT
V
CCO
V
REF
V
IN
V
TS
T
STG
T
J
Description
Supply voltage relative to GND
(2)
Supply voltage relative to GND
(2)
Input reference voltage
Input voltage relative to GND
(3)
Voltage applied to 3-state output
Storage temperature (ambient)
Junction temperature
5V tolerant I/O
(4)
No 5V tolerance
(5)
5V tolerant I/O
(4)
No 5V tolerance
(5)
Min
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–65
-
Max
3.0
4.0
3.6
5.5
V
CCO
+ 0.5
5.5
V
CCO
+ 0.5
+150
+135
Units
V
V
V
V
V
V
V
°
C
°
C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
2. Power supplies may turn on in any order.
3. V
IN
should not exceed V
CCO
by more than 3.6V over extended periods of time (e.g., longer than a day).
4. Spartan-II I/Os are 5V Tolerant whenever the LVTTL, LVCMOS2, or PCI33_5 signal standard has been selected. With 5V Tolerant
I/Os selected, the Maximum DC overshoot must be limited to either +5.5V or 10 mA, and undershoot must be limited to either –0.5V
or 10 mA, whichever is easier to achieve. The Maximum AC conditions are as follows: The device pins may undershoot to –2.0V or
overshoot to +7.0V, provided this over/undershoot lasts no more than 11 ns with a forcing current no greater than 100 mA.
5. Without 5V Tolerant I/Os selected, the Maximum DC overshoot must be limited to either V
CCO
+ 0.5V or 10 mA, and undershoot
must be limited to –0.5V or 10 mA, whichever is easier to achieve. The Maximum AC conditions are as follows: The device pins may
undershoot to –2.0V or overshoot to V
CCO
+ 2.0V, provided this over/undershoot lasts no more than 11 ns with a forcing current no
greater than 100 mA.
6. For soldering guidelines, see the Packaging Information on the Xilinx website:
www.xilinx.com/partinfo/pkgs.htm
Recommended Operating Conditions
Symbol
T
J
V
CCINT
V
CCO
T
IN
Description
Junction temperature
Supply voltage relative to GND
(1,2)
Supply voltage relative to GND
(2,3)
Input signal transition time
(4)
Min
–40
2.5 – 5%
1.4
-
Max
125
2.5 + 5%
3.6
250
Units
°
C
V
V
ns
Notes:
1. Functional operation is guaranteed down to a minimum V
CCINT
of 2.25V (Nominal V
CCINT
– 10%). For every 50 mV reduction in
V
CCINT
below 2.375V (nominal V
CCINT
– 5%), all delay parameters increase by 3%.
2. Supply voltages may be applied in any order desired.
3. Minimum and maximum values for V
CCO
vary according to the I/O standard selected.
4. Input and output measurement threshold is ~50% of V
CCO
.
DC Characteristics Over Operating Conditions
Symbol
I
CCINTQ
Description
Quiescent V
CCINT
supply current
(1)
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
Min
-
-
-
-
-
-
Max
60
115
125
140
165
200
Units
mA
mA
mA
mA
mA
mA
Notes:
1. With no output current loads, no active input pull-up resistors, all I/O pins 3-stated and floating.
2
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DS105-1 (v1.4) October 18, 2004
Product Specification
R
Spartan-II 2.5V FPGA Automotive IQ Product Family: Introduction and Ordering Information
Spartan-II Product Availability
Table 2
shows the package and speed grades available for
Spartan-II family devices.
Table 3
shows the maximum user
I/Os available on the device and the number of user I/Os
available for each device/package combination. The four
global clock pins are usable as additional user I/Os when
not used as a global clock pin. These pins are not included
in user I/O counts.
Table 2:
Spartan-II Package and Speed Grade Availability
Pins
100
208
Type
Device
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
Code
-5
-5
-5
-5
-5
-5
Plastic VQFP
VQ100
Q
-
-
-
-
-
Plastic PQFP
PQ208
-
Q
Q
Q
Q
Q
256
Fine Pitch
BGA
FG256
-
-
Q
Q
Q
-
456
Fine Pitch
BGA
FG456
-
-
-
-
-
Q
144
Plastic TQFP
TQ144
Q
Q
Q
Q
-
-
Notes:
1. Q= Automotive IQ, T
J
= –40° C to +125° C.
Table 3:
Spartan-II User I/O Chart
(1)
Available User I/O According to Package Type
Device
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
Maximum
User I/O
86
132
176
176
176
284
VQ100
60
-
-
-
-
-
TQ144
86
92
92
92
-
-
PQ208
-
132
140
140
140
140
FG256
-
-
176
176
176
-
FG456
-
-
-
-
-
284
Notes:
1. All user I/O counts do not include the four global clock/user input pins.
DS105-1 (v1.4) October 18, 2004
Product Specification
www.xilinx.com
1-800-255-7778
3
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