A3PN030-Z1QNG68 datasheet, PDF

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A3PN030-Z1QNG68: Descriptionfpga - field programmable gate array 30k system gates proasic3 nano; CategoryProgrammable logic devices Programmable logic; File Size4MB，106 Pages; ManufacturerActel; Websitehttp://www.actel.com/; Environmental Compliance

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A3PN030-Z1QNG68 Overview

fpga - field programmable gate array 30k system gates proasic3 nano

A3PN030-Z1QNG68 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Actel
package instruction	8 X 8 MM, 0.90 MM HEIGHT, 0.40 MM PITCH, ROHS COMPLIANT, QFN-68
Reach Compliance Code	compliant
JESD-30 code	S-XQCC-N68
JESD-609 code	e3
length	8 mm
Humidity sensitivity level	3
Configurable number of logic blocks	768
Equivalent number of gates	30000
Number of entries	49
Number of logical units	768
Output times	49
Number of terminals	68
Maximum operating temperature	70 °C
Minimum operating temperature	-20 °C
organize	768 CLBS, 30000 GATES
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Encapsulate equivalent code	LCC68,.32SQ,16
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
power supply	1.5,1.5/3.3 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	1 mm
Maximum supply voltage	1.575 V
Minimum supply voltage	1.425 V
Nominal supply voltage	1.5 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	MATTE TIN
Terminal form	NO LEAD
Terminal pitch	0.4 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	8 mm

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Revision 8

ProASIC3 nano Flash FPGAs

Features and Benefits

Wide Range of Features

• 10 k to 250 k System Gates

• Up to 36 kbits of True Dual-Port SRAM

• Up to 71 User I/Os

Advanced I/Os

• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V

• Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

• I/O Registers on Input, Output, and Enable Paths

• Selectable Schmitt Trigger Inputs

• Hot-Swappable and Cold-Sparing I/Os

• Programmable Output Slew Rate

†

and Drive Strength

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the ProASIC3 Family

†

• Up to Six CCC Blocks, One with an Integrated PLL

• Configurable Phase Shift, Multiply/Divide, Delay

Capabilities and External Feedback

• Wide Input Frequency Range (1.5 MHz to 350 MHz)

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS

Process

• Live at Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

• Retains Programmed Design when Powered Off

High Performance

• 350 MHz System Performance

In-System Programming (ISP) and Security

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

Standard (AES) Decryption via JTAG (IEEE 1532–compliant)

†

• FlashLock

to Secure FPGA Contents

Clock Conditioning Circuit (CCC) and PLL

Low Power

•

Embedded Memory

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

†

• True Dual-Port SRAM (except ×18 organization)

†

Low Power ProASIC 3 nano Products

1.5 V Core Voltage for Low Power

Support for 1.5 V-Only Systems

Low-Impedance Flash Switches

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

Enhanced Commercial Temperature Range

• –20°C to +70°C

Table 1 • ProASIC3 nano Devices

ProASIC3 nano Devices

ProASIC3 nano-Z Devices

System Gates

Typical Equivalent Macrocells

VersaTiles (D-flip-flops)

RAM Kbits (1,024 bits)

4,608-Bit Blocks

FlashROM Kbits

Secure (AES) ISP

Integrated PLL in CCCs

VersaNet Globals

I/O Banks

Maximum User I/Os (packaged device)

Maximum User I/Os (Known Good Die)

Package Pins

QFN

VQFP

10,000

260

–

QN48

15,000

128

384

–

QN68

20,000

172

520

–

QN68

A3PN010

A3PN015

A3PN020

A3PN030Z

30,000

256

768

–

QN48, QN68

VQ100

A3PN060

A3PN125

A3PN250

A3N250Z

250,000

2,048

6,144

Yes

A3PN060Z A3PN125Z

60,000

512

1,536

Yes

125,000

1,024

3,072

Yes

VQ100

Notes:

1. A3PN030 is available in the Z feature grade only.

2. A3PN030 and smaller devices do not support this feature.

3. For higher densities and support of additional features, refer to the

ProASIC3

and

ProASIC3E

datasheets.

† A3PN030 and smaller devices do not support this feature.

April 2010

ProASIC3 nano Flash FPGAs

Table of Contents

ProASIC3 nano Device Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

ProASIC3 nano DC and Switching Characteristics

General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12

VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49

Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53

Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57

Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59

Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-69

JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70

Actel Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70

Package Pin Assignments

48-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

68-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

100-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

Actel Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

Revision 8

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