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A1425A-PQ100I

Description
fpga - field programmable gate array 2.5K system gates
CategoryProgrammable logic devices    Programmable logic   
File Size333KB,54 Pages
ManufacturerActel
Websitehttp://www.actel.com/
Download Datasheet Parametric View All

A1425A-PQ100I Overview

fpga - field programmable gate array 2.5K system gates

A1425A-PQ100I Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
package instructionPLASTIC, QFP-100
Reach Compliance Codecompliant
Other featuresMAX 80 I/OS
maximum clock frequency116.8 MHz
Combined latency of CLB-Max3 ns
JESD-30 codeR-PQFP-G100
JESD-609 codee0
length20 mm
Humidity sensitivity level3
Configurable number of logic blocks310
Equivalent number of gates2500
Number of entries100
Number of logical units310
Output times100
Number of terminals100
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize310 CLBS, 2500 GATES
Package body materialPLASTIC/EPOXY
encapsulated codeQFP
Encapsulate equivalent codeQFP100,.7X.9
Package shapeRECTANGULAR
Package formFLATPACK
Peak Reflow Temperature (Celsius)225
power supply5 V
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height3.4 mm
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width14 mm
Base Number Matches1
v3.1
RadTolerant FPGAs
Features
General Characteristics
Tested Total Ionizing Dose (TID) Survivability Level
No Single Event Latch-Up Below a Minimum LET
(Linear Energy Transfer) Threshold of 80 MeV-cm
2
/mg
for All RT (RadTolerant) Devices
Packages: 84-Pin, 132-Pin, 172-Pin, 196-Pin, and
256-Pin Ceramic Quad Flat Pack
Offered as Class B and E-Flow (Actel Space Level
Flow)
QML Certified Devices
100% Military Temperature Tested (–55°C to
+125°C)
Up to 60 MHz System Performance
Up to 228 User I/Os
Up to Four Fast, Low-Skew Clock Networks
Easy Logic Integration
Nonvolatile, User Programmable
Pin-Compatible Commercial Devices Available for
Prototyping
Highly Predictable Performance with 100%
Automatic Place-and-Route
100% Resource Utilization with 100% Pin-Locking
Secure Programming Technology Prevents Reverse
Engineering and Design Theft
Permanently Programmed for Operation on
Power-Up
Unique In-System Diagnostic and Verification
Capability with Silicon Explorer
High Density and Performance
4,000 to 20,000 Logic Equivalent Gates
2,000 to 10,000 ASIC Equivalent Gates
Up to 85 MHz Internal Performance
Product Family Profile
Table 1 •
Device
Capacity
System Gates
Logic Gates
ASIC Equivalent Gates
PLD Equivalent Gates
TTL Equivalent Package
20-Pin PAL Equivalent Packages
Logic Modules
S-Modules
C-Modules
User I/Os (Maximum)
Performance
System Speed (Maximum)
Packages (by Pin Count)
CQFP
RadTolerant Family
RT1020
6,000
4,000
2,000
5,000
50
20
547
N/A
547
69
20 MHz
84
RT1280A
24,000
16,000
8.000
20,000
200
80
1,232
624
608
140
40 MHz
172
RT1425A
7,500
5,000
2,500
6,250
60
25
310
160
150
100
60 MHz
132
RT1460A
18,000
12,000
6,000
15.000
150
60
848
432
416
168
60 MHz
196
RT14100A
30,000
20,000
10,000
25,000
250
100
1,377
697
680
228
60 MHz
256
October 2004
© 2004 Actel Corporation
i
See Actel’s website for the latest version of the datasheet

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