DC to 2.0 GHz
Multiplier
ADL5391
FEATURES
Ultrafast symmetric multiplier
Function: V
W
= α × (V
X
× V
Y
)/1 V + V
Z
Unique design ensures absolute XY-symmetry
Identical X and Y amplitude/timing responses
Adjustable gain scaling, α
DC-coupled throughout, 3 dB bandwidth of 2 GHz
Fully differential inputs, may be used single ended
Low noise, high linearity
Accurate, temperature stable gain scaling
Single-supply operation (4.5 V to 5.5 V @ 130 mA)
Low current power-down mode
16-lead LFCSP
FUNCTIONAL BLOCK DIAGRAM
YMNS YPLS
GADJ
XPLS
XMNS
ZMNS
ZPLS
WPLS
ENBL
VMID
WMNS
ADL5391
COMM VPOS
06059-001
W =
αXY/1V+Z
Figure 1.
APPLICATIONS
Wideband multiplication and summing
High frequency analog modulation
Adaptive antennas (diversity/phased array)
Square-law detectors and true rms detectors
Accurate polynomial function synthesis
DC capable VGA with very fast control
GENERAL DESCRIPTION
The ADL5391 draws on three decades of experience in
advanced analog multiplier products. It provides the same
general mathematical function that has been field proven to
provide an exceptional degree of versatility in function synthesis.
V
W
=
α
× (V
X
×
V
Y
)/ 1 V +
V
Z
The most significant advance in the ADL5391 is the use of a
new multiplier core architecture, which differs markedly from
the conventional form that has been in use since 1970. The
conventional structure that employs a current mode, translinear
core is fundamentally asymmetric with respect to the X and Y
inputs, leading to relative amplitude and timing misalignments
that are problematic at high frequencies. The new multiplier
core eliminates these misalignments by offering symmetric
signal paths for both X and Y inputs. The Z input allows a signal
to be added directly to the output. This can be used to cancel a
carrier or to apply a static offset voltage.
The fully differential X, Y, and Z input interfaces are operational
over a ±2 V range, and they can be used in single-ended fashion.
The user can apply a common mode at these inputs to vary
from the internally set V
POS
/2 down to ground. If these inputs
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
are ac-coupled, their nominal voltage will be V
POS
/2. These input
interfaces each present a differential 500 Ω input impedance up to
approximately 700 MHz, decreasing to 50 Ω at 2 GHz. The gain
scaling input, GADJ, can be used for fine adjustment of the gain
scaling constant (α) about unity.
The differential output can swing ±2 V about the V
POS
/2
common-mode and can be taken in a single-ended fashion as
well. The output common mode is designed to interface directly
to the inputs of another ADL5391. Light dc loads can be ground
referenced; however, ac-coupling of the outputs is recommended
for heavy loads.
The ENBL pin allows the ADL5391 to be disabled quickly to a
standby mode. It operates off supply voltages from 4.5 V to
5.5 V while consuming approximately 130 mA.
The ADL5391 is fabricated on Analog Devices proprietary, high
performance, 65 GHz, SOI complementary, SiGe bipolar IC
process. It is available in a 16-lead, Pb-free, LFCSP and operates
over a −40°C to +85°C temperature range. Evaluation boards
are available.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
ADL5391
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ..............................................7
General Description....................................................................... 10
Basic Theory ............................................................................... 10
Basic Connections...................................................................... 10
Evaluation Board ............................................................................ 13
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 15
REVISION HISTORY
7/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADL5391
SPECIFICATIONS
V
POS
= 5 V, T
A
= 25°C, Z
L
= 50 Ω differential, ZPLS = ZMNS = open, GADJ = open, unless otherwise noted. Transfer function: W =
XY/1 V + Z, common mode internally set to 2.5 V nominal.
Table 1.
Parameter
MULTIPLICAND INPUTS (X, Y)
Differential Voltage Range
Common-Mode Range
Input Offset Voltage
vs. Temperature
Differential Input Impedance
Fundamental Feedthrough, X or Y
Conditions
XPLS, XMNS, YPLS, YMNS
Differential, common mode = 2.5 V
For full differential range
DC
−40°C to +85°C
f = dc
f = 2 GHz
f = 50 MHz, X (Y) = 0 V, Y (X) = 0 dBm, relative to
condition where X (Y) = 1 V
f = 1 GHz
X = 50 MHz and 0 dBm, Y = 1 V
X = 1 GHz and 0 dBm, Y = 1 V
X to output, Y = 1 V
X=Y=1V
±1 V p-p, Y = 1 V, f = 50 MHz
ZPLS, ZMNS
Common mode from 2.5 V down to COMM
For full differential range
From Z to W, f ≤ 10 MHz, 0 dBm, X = Y = 1 V
f = dc
f = 2 GHz
WPLS, WMNS
No external common mode
X = Y = 1 V dc
f = 1 MHz
f = 1 GHz
X=Y=0
f = 1 MHz
f = 1 GHz
X = Y = 0, f = 1 MHz
Z = 0 V differential
f = dc
f = 200 MHz
f = 2 GHz
X, Y, Z to W
W from −2.0 V to +2.0 V, 150 Ω
X stepped from −1 V to +1 V, Z = 0 V, 150 Ω
X (Y) = 0 dBm, Y (X) = 1 V, fund = 10 MHz
Fund = 200 MHz
X (Y) = 0 dBm, Y (X) = 1 V, fund = 10 MHz
Fund = 200 MHz
0
8800
2.1
−60
−51
−61.5
−51.6
Min
Typ
2
0
20
±20
500
150
−42
−35
0.5
−1.33
1
1
42.1
2
0
0.1
500
150
±2
V
POS
− 2.5
−133
−133
−138
−138
26.7
19
±19
0
75
500
2
2.5
2.5
Max
Unit
V p-p
V
mV
mV
Ω
Ω
dB
dB
dB
dB
% FS
V/V
dB
V p-p
V
dB
Ω
Ω
V
V
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
nV/√Hz
mV
mV
Ω
Ω
Ω
GHz
V/μs
ns
dBc
dBc
dBc
dBc
Gain
DC Linearity
Scale Factor
CMRR
SUMMING INPUT (Z)
Differential Voltage Range
Common-Mode Range
Gain
Differential Input Impedance
OUTPUTS (W)
Differential Voltage Range
Common-Mode Output
Output Noise Floor
Output Noise Voltage Spectral Density
Output Offset Voltage
vs. Temperature
Differential Output Impedance
DYNAMIC CHARACTERISTICS
Frequency Range
Slew Rate
Settling Time
Second Harmonic Distortion
Third Harmonic Distortion
Rev. 0 | Page 3 of 16
ADL5391
Parameter
OIP3
Conditions
Two-tone IP3 test; X (Y) = 100 mV p-p/tone
(−10 dBm into 50 Ω), Y (X) = 1
f1= 49 MHz, f = 50 MHz
f1 = 999 MHz, f2 = 1 GHz
f1 = 49 MHz, f = 50 MHz
f1 = 999 MHz, f2 = 1 GHz
X (Y) to W, Y (X) = 1 V, 50 MHz
1 GHz
200 MHz
1 GHz
f = 3.58 MHz
f = 3.58 MHz
GADJ
Unconnected
Input 0 V to 2 V
VMID
Common-mode for X, Y, Z = 2.5 V
V
POS
, COMM, ENBL
4.5
Common-mode for X, Y, Z = 2.5 V
ENBL = 0 V
High to Low
Delay following high-to-low transition until device
meets full specifications
Delay following low-to-high transition until device
produces full attenuation
135
7.5
1.5
150
50
Min
Typ
Max
Unit
OIP2
Output 1 dB Compression Point
Group Delay
Differential Gain Error, X/Y
Differential Phase Error, X/Y
GAIN TRIMMING (α)
Nominal Bias
Input Range
Gain Adjust Range
REFERENCE VOLTAGE
Source Current
POWER AND ENABLE
Supply Voltage Range
Total Supply Current
Disable Current
Disable Threshold
Enable Response Time
Disable Response Time
26.5
14
45.5
28
15.1
13.2
0.5
0.7
2.7
0.23
1.12
0
9.5
V
POS
/2
50
5.5
2
dBm
dBm
dBm
dBm
dBm
dBm
ns
ns
%
Degrees
V
V
dB
V
mA
V
mA
mA
V
ns
ns
Rev. 0 | Page 4 of 16
ADL5391
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage V
POS
ENBL
XPLS, XMNS, YPLS, YMNS, ZPLS, ZMNS
GADJ
Internal Power Dissipation
θ
JA
(With Pad Soldered to Board)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering 60 sec)
Rating
5.5 V
5.5 V
V
POS
V
POS
800 mW
73°C/W
150°C
−40°C to +85°C
−65°C to +150°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 5 of 16
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