Intel
®
Xeon
™
Processor with 512 KB L2 Cache
at 1.80 GHz to 2.80 GHz
Datasheet
Product Features
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Available at 1.80, 2, 2.20, 2.40, 2.60, and
2.80 GHz
Dual processing server/workstation support
Binary compatible with applications running on
previous members of Intel’s IA32
microprocessor line
Intel
®
NetBurst™ micro-architecture
Hyper-Threading Technology
— Hardware support for multithreaded
applications
400 MHz System bus
— Bandwidth up to 3.2 GB/second
Rapid Execution Engine: Arithmetic Logic
Units (ALUs) run at twice the processor core
frequency
Hyper Pipelined Technology
Advance Dynamic Execution
— Very deep out-of-order execution
— Enhanced branch prediction
Level 1 Execution Trace Cache stores 12 K
micro-ops and removes decoder latency from
main execution loops
— Includes 8 KB Level 1 data cache
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512 KB Advanced Transfer L2 Cache (on-die,
full speed Level 2 cache) with 8-way
associativity and Error Correcting Code (ECC)
Enables system support of up to 64 GB of
physical memory
Streaming SIMD Extensions 2 (SSE2)
— 144 new instructions for double-precision
floating point operations, media/video
streaming, and secure transactions
Enhanced floating point and multimedia unit for
enhanced video, audio, encryption, and 3D
performance
Power Management capabilities
— System Management mode
— Multiple low-power states
Advanced System Management Features
— System Management Bus
— Processor Information ROM (PIROM)
— OEM Scratch EEPROM
— Thermal Monitor
— Machine Check Architecture (MCA)
The Intel
®
Xeon™ processor with 512 KB L2 cache is designed for high-performance dual-
processor workstation and server applications. Based on the Intel
®
NetBurst™ micro-
architecture and the new Hyper-Threading Technology, it is binary compatible with previous
Intel Architecture (IA-32) processors. The Intel Xeon processor with 512 KB L2 cache is
scalable to two processors in a multiprocessor system providing exceptional performance for
applications running on advanced operating systems such as Windows XP*, Windows* 2000,
Linux*, and UNIX*. The Intel Xeon processor with 512 KB L2 cache delivers compute power at
unparalleled value and flexibility for powerful workstations, internet infrastructure, and
departmental server applications. The Intel
®
NetBurst™ micro-architecture and Hyper-
Threading Technology deliver outstanding performance and headroom for peak internet server
workloads, resulting in faster response times, support for more users, and improved scalability.
Order Number: 298642-005
Sept 2002
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS
OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS
DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL
ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO
SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A
PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to them.
The Intel
®
Xeon
™
processor may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained
by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Intel, Pentium, Pentium III Xeon, Intel Xeon and Intel NetBurst are trademark or registered trademarks of Intel Corporation or its
subsidiaries in the United States and other countries.
Copyright © Intel Corporation, 2002
Datasheet
Contents
Contents
1.0
Introduction...................................................................................................................................... 9
1.1
Terminology ......................................................................................................................10
1.1.1 Processor Packaging Terminology ..................................................................... 10
1.2
State of Data.....................................................................................................................11
1.3
References .......................................................................................................................12
Electrical Specifications .................................................................................................................13
2.1
System Bus and GTLREF ................................................................................................13
2.2
Power and Ground Pins ...................................................................................................13
2.3
Decoupling Guidelines......................................................................................................13
2.3.1 VCC Decoupling ................................................................................................. 14
2.3.2 System Bus AGTL+ Decoupling ......................................................................... 14
2.4
System Bus Clock (BCLK[1:0]) and Processor Clocking..................................................14
2.4.1 Bus Clock............................................................................................................ 15
2.5
PLL Filter ..........................................................................................................................15
2.5.1 Mixing Processors .............................................................................................. 17
2.6
Voltage Identification .......................................................................................................18
2.6.1 Mixing Processors of Different Voltages............................................................. 19
2.7
Reserved Or Unused Pins ................................................................................................20
2.8
System Bus Signal Groups...............................................................................................20
2.9
Asynchronous GTL+ Signals ............................................................................................22
2.10
Maximum Ratings .............................................................................................................22
2.11
Processor DC Specifications ............................................................................................23
2.12
AGTL+ System Bus Specifications...................................................................................28
2.13
System Bus AC Specifications .........................................................................................29
2.14
Processor AC Timing Waveforms.....................................................................................32
System Bus Signal Quality Specifications .....................................................................................41
3.1
System Bus Clock (BCLK) Signal Quality Specifications and Measurement Guidelines .41
3.2
System Bus Signal Quality Specifications and Measurement Guidelines ........................42
3.3
System Bus Signal Quality Specifications and Measurement Guidelines ........................46
3.3.1 Overshoot/Undershoot Guidelines...................................................................... 46
3.3.2 Overshoot/Undershoot Magnitude...................................................................... 46
3.3.3 Overshoot/Undershoot Pulse Duration ............................................................... 46
3.3.4 Activity Factor ..................................................................................................... 47
3.3.5 Reading Overshoot/Undershoot Specification Tables ........................................ 47
3.3.6 Determining if a System Meets the Overshoot/Undershoot Specifications ........ 48
Mechanical Specifications .............................................................................................................53
4.1
Mechanical Specifications ................................................................................................54
4.2
Processor Package Load Specifications ..........................................................................58
4.3
Insertion Specifications.....................................................................................................59
4.4
Mass Specifications ..........................................................................................................59
4.5
Materials ...........................................................................................................................59
4.6
Markings ...........................................................................................................................60
4.7
Pin-Out Diagram ...............................................................................................................61
Pin Listing and Signal Definitions ..................................................................................................63
5.1
Processor Pin Assignments..............................................................................................63
5.1.1 Pin Listing by Pin Name...................................................................................... 63
5.1.2 Pin Listing by Pin Number .................................................................................. 72
2.0
3.0
4.0
5.0
Datasheet
3
Contents
6.0
7.0
8.0
9.0
5.2
Signal Definitions.............................................................................................................. 80
Thermal Specifications .................................................................................................................. 91
6.1
Thermal Specifications ..................................................................................................... 92
6.2
Measurements for Thermal Specifications ....................................................................... 93
6.2.1 Processor Case Temperature Measurement ..................................................... 93
Features ........................................................................................................................................ 95
7.1
Power-On Configuration Options...................................................................................... 95
7.2
Clock Control and Low Power States ............................................................................... 95
7.2.1 Normal State—State 1........................................................................................ 95
7.2.2 AutoHALT Powerdown State—State 2............................................................... 96
7.2.3 Stop-Grant State—State 3.................................................................................. 97
7.2.4 HALT/Grant Snoop State—State 4..................................................................... 97
7.2.5 Sleep State—State 5 .......................................................................................... 97
7.2.6 Bus Response During Low Power States........................................................... 98
7.3
Thermal Monitor ............................................................................................................... 98
7.3.1 Thermal Diode .................................................................................................... 99
7.4
System Management Bus (SMBus) Interface .................................................................. 99
7.4.1 Processor Information ROM (PIROM) .............................................................. 100
7.4.2 Scratch EEPROM............................................................................................. 103
7.4.3 PIROM and Scratch EEPROM Supported SMBus Transactions ..................... 103
7.4.4 SMBus Thermal Sensor ................................................................................... 103
7.4.5 Thermal Sensor Supported SMBus Transactions ............................................ 104
7.4.6 SMBus Thermal Sensor Registers ................................................................... 106
7.4.7 SMBus Thermal Sensor Alert Interrupt............................................................. 108
7.4.8 SMBus Device Addressing ............................................................................... 109
Boxed Processor Specifications .................................................................................................. 111
8.1
Introduction..................................................................................................................... 111
8.2
Mechanical Specifications .............................................................................................. 111
8.2.1 Boxed Processor Heatsink Dimensions ........................................................... 112
8.2.2 Boxed Processor Heatsink Weight ................................................................... 112
8.2.3 Boxed Processor Retention Mechanism and Heatsink Supports ..................... 112
8.3
Boxed Processor Requirements..................................................................................... 115
8.3.1 Intel® Xeon™ Processor with 512 KB L2 Cache ............................................. 115
8.4
Thermal Specifications ................................................................................................... 117
8.4.1 Boxed Processor Cooling Requirements.......................................................... 117
Debug Tools Specifications ......................................................................................................... 119
9.1
Logic Analyzer Interface (LAI) ........................................................................................ 119
9.1.1 Mechanical Considerations .............................................................................. 119
9.1.2 Electrical Considerations .................................................................................. 119
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Datasheet
Contents
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Typical VCCIOPLL, VCCA and VSSA Power Distribution ........................................................16
Phase Lock Loop (PLL) Filter Requirements ............................................................................17
Intel® Xeon™ Processor with 512 KB L2 Cache Voltage-Current Projections ........................25
Electrical Test Circuit.................................................................................................................33
TCK Clock Waveform................................................................................................................33
Differential Clock Waveform......................................................................................................34
System Bus Common Clock Valid Delay Timing Waveform .....................................................34
System Bus Source Synchronous 2X (Address) Timing Waveform..........................................35
System Bus Source Synchronous 4X (Data) Timing Waveform ...............................................36
System Bus Reset and Configuration Timing Waveform ..........................................................37
Power-On Reset and Configuration Timing Waveform .............................................................37
TAP Valid Delay Timing Waveform ...........................................................................................38
Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform .........................38
THERMTRIP# to VCC Timing ...................................................................................................38
SMBus Timing Waveform..........................................................................................................39
SMBus Valid Delay Timing Waveform ......................................................................................39
Example 3.3 VDC/SM_VCC Sequencing..................................................................................40
BCLK[1:0] Signal Integrity Waveform........................................................................................42
Low-to-High System Bus Receiver Ringback Tolerance for AGTL+ and Asynchronous GTL+
43
High-to-Low System Bus Receiver Ringback Tolerance for AGTL+ and Asynchronous GTL+
44
Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD TAP Buffers.............44
High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and TAP Buffers......45
Maximum Acceptable Overshoot/Undershoot Waveform .........................................................51
INT-mPGA Processor Package Assembly Drawing (Includes Socket) .....................................53
INT-mPGA Processor Package Top View: Component Placement Detail................................54
INT-mPGA Processor Package Drawing ..................................................................................55
INT-mPGA Processor Package Top View: Component Height Keep-in ...................................56
INT-mPGA Processor Package Cross Section View: Pin Side Component Keep-in ................56
INT-mPGA Processor Package: Pin Detail ...............................................................................57
IHS Flatness and Tilt Drawing...................................................................................................58
Processor Top-Side Markings ...................................................................................................60
Processor Bottom-Side Markings..............................................................................................60
Processor Pin Out Diagram: Top View......................................................................................61
Processor Pin Out Diagram: Bottom View ................................................................................62
Processor with Thermal and Mechanical Components - Exploded View ..................................91
Thermal Measurement Point for Processor TCASE..................................................................93
Stop Clock State Machine .........................................................................................................96
Logical Schematic of SMBus Circuitry ....................................................................................100
Mechanical Representation of the Boxed Processor Passive Heatsink..................................111
Boxed Processor Retention Mechanism and Clip ...................................................................113
Multiple View Space Requirements for the Boxed Processor .................................................114
Processor Wind Tunnel General Dimensions .........................................................................116
Processor Wind Tunnel Detailed Dimensions .........................................................................118
Datasheet
5
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