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BUK98150-55

Description
trenchmos transistor logic level fet
CategoryDiscrete semiconductor    The transistor   
File Size69KB,9 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Environmental Compliance
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BUK98150-55 Overview

trenchmos transistor logic level fet

BUK98150-55 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerNXP
Parts packaging codeSC-73
package instructionPLASTIC, SC-73, 4 PIN
Contacts4
Reach Compliance Codecompliant
ECCN codeEAR99
Other featuresLOGIC LEVEL COMPATIBLE, ESD PROTECTED
Avalanche Energy Efficiency Rating (Eas)15 mJ
Shell connectionDRAIN
ConfigurationSINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage55 V
Maximum drain current (Abs) (ID)5.5 A
Maximum drain current (ID)2.6 A
Maximum drain-source on-resistance0.15 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
JESD-30 codeR-PDSO-G4
JESD-609 codee3
Humidity sensitivity level1
Number of components1
Number of terminals4
Operating modeENHANCEMENT MODE
Maximum operating temperature150 °C
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Polarity/channel typeN-CHANNEL
Maximum power dissipation(Abs)1.8 W
Maximum pulsed drain current (IDM)30 A
Certification statusNot Qualified
surface mountYES
Terminal surfaceTin (Sn)
Terminal formGULL WING
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
transistor applicationsSWITCHING
Transistor component materialsSILICON
Base Number Matches1
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope suitable for surface
mounting. The device features very
low on-state resistance and has
integral zener diodes giving ESD
protection. It is intended for use in
automotive and general purpose
switching applications.
BUK98150-55
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
tot
T
j
R
DS(ON)
PARAMETER
Drain-source voltage
Drain current
Total power dissipation
Junction temperature
Drain-source on-state
resistance
V
GS
= 5 V
MAX.
55
5.5
1.8
150
150
UNIT
V
A
W
˚C
mΩ
PINNING - SOT223
PIN
1
2
3
4
gate
drain
source
drain (tab)
DESCRIPTION
PIN CONFIGURATION
4
SYMBOL
d
g
s
1
2
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
V
DS
V
DGR
±V
GS
I
D
I
D
I
D
I
DM
P
tot
P
tot
T
stg
, T
j
PARAMETER
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Total power dissipation
Storage & operating temperature
CONDITIONS
-
R
GS
= 20 kΩ
-
T
sp
= 25 ˚C
On PCB in Fig.19
T
amb
= 25 ˚C
On PCB in Fig.19
T
amb
= 100 ˚C
T
sp
= 25 ˚C
T
sp
= 25 ˚C
On PCB in Fig.19
T
amb
= 25 ˚C
-
MIN.
-
-
-
-
-
-
-
-
-
- 55
MAX.
55
55
10
5.5
2.6
1.6
30
8.3
1.8
150
UNIT
V
V
V
A
A
A
A
W
W
˚C
ESD LIMITING VALUE
SYMBOL
V
C
PARAMETER
Electrostatic discharge capacitor
voltage
CONDITIONS
Human body model
(100 pF, 1.5 kΩ)
MIN.
-
MAX.
2
UNIT
kV
February 1998
1
Rev 1.000
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