Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope suitable for surface
mounting. The device features very
low on-state resistance and has
integral zener diodes giving ESD
protection. It is intended for use in
automotive and general purpose
switching applications.
BUK9880-55
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
tot
T
j
R
DS(ON)
PARAMETER
Drain-source voltage
Drain current
Total power dissipation
Junction temperature
Drain-source on-state
resistance
V
GS
= 5 V
MAX.
55
7.5
1.8
150
80
UNIT
V
A
W
˚C
mΩ
PINNING - SOT223
PIN
1
2
3
4
gate
drain
source
drain (tab)
DESCRIPTION
PIN CONFIGURATION
4
SYMBOL
d
g
s
1
2
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
V
DS
V
DGR
±V
GS
I
D
I
D
I
D
I
DM
P
tot
P
tot
T
stg
, T
j
PARAMETER
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Total power dissipation
Storage & operating temperature
CONDITIONS
-
R
GS
= 20 kΩ
-
T
sp
= 25 ˚C
On PCB in Fig.2
T
amb
= 25 ˚C
On PCB in Fig.2
T
amb
= 100 ˚C
T
sp
= 25 ˚C
T
sp
= 25 ˚C
On PCB in Fig.2
T
amb
= 25 ˚C
-
MIN.
-
-
-
-
-
-
-
-
-
- 55
MAX.
55
55
10
7.5
3.5
2.2
40
8.3
1.8
150
UNIT
V
V
V
A
A
A
A
W
W
˚C
ESD LIMITING VALUE
SYMBOL
V
C
PARAMETER
Electrostatic discharge capacitor
voltage
CONDITIONS
Human body model
(100 pF, 1.5 kΩ)
MIN.
-
MAX.
2
UNIT
kV
April 1998
1
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
THERMAL RESISTANCES
SYMBOL
R
th j-sp
R
th j-amb
PARAMETER
From junction to solder point
From junction to ambient
CONDITIONS
Mounted on any PCB
Mounted on PCB of Fig.18
TYP.
12
-
BUK9880-55
MAX.
15
70
UNIT
K/W
K/W
STATIC CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL
V
(BR)DSS
V
GS(TO)
I
DSS
I
GSS
±V
(BR)GSS
R
DS(ON)
PARAMETER
Drain-source breakdown
voltage
Gate threshold voltage
Zero gate voltage drain current
Gate source leakage current
CONDITIONS
V
GS
= 0 V; I
D
= 0.25 mA
T
j
= -55˚C
V
DS
= V
GS
; I
D
= 1 mA
T
j
= 150˚C
T
j
= -55˚C
V
DS
= 55 V; V
GS
= 0 V;
V
GS
=
±5
V
T
j
= 150˚C
T
j
= 150˚C
T
j
= 150˚C
MIN.
55
50
1.0
0.6
-
-
-
-
-
10
-
-
TYP.
-
-
1.5
-
-
0.05
-
0.02
-
-
65
-
MAX.
-
-
2.0
-
2.3
10
100
1
5
-
80
148
UNIT
V
V
V
V
V
µA
µA
µA
µA
V
mΩ
mΩ
Gate source breakdown voltage I
G
=
±1
mA
Drain-source on-state
V
GS
= 5 V; I
D
= 5 A
resistance
DYNAMIC CHARACTERISTICS
T
mb
= 25˚C unless otherwise specified
SYMBOL
g
fs
C
iss
C
oss
C
rss
t
d on
t
r
t
d off
t
f
PARAMETER
Forward transconductance
Input capacitance
Output capacitance
Feedback capacitance
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
CONDITIONS
V
DS
= 25 V; I
D
= 5 A; T
j
= 25˚C
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
MIN.
4
-
-
-
-
-
-
-
TYP.
8
500
110
60
10
30
30
30
MAX.
-
650
135
85
15
50
45
40
UNIT
S
pF
pF
pF
ns
ns
ns
ns
V
DD
= 30 V; I
D
= 7 A;
V
GS
= 5 V; R
G
= 10
Ω;
T
j
= 25˚C
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= -55 to 175˚C unless otherwise specified
SYMBOL
I
DR
I
DRM
V
SD
t
rr
Q
rr
PARAMETER
Continuous reverse drain
current
Pulsed reverse drain current
Diode forward voltage
Reverse recovery time
Reverse recovery charge
CONDITIONS
T
sp
= 25˚C
T
sp
= 25˚C
I
F
= 5 A; V
GS
= 0 V
I
F
= 5 A; -dI
F
/dt = 100 A/µs;
V
GS
= -10 V; V
R
= 30 V
MIN.
-
-
-
-
-
TYP.
-
-
0.85
38
0.2
MAX.
7.5
40
1.1
-
-
UNIT
A
A
V
ns
µC
April 1998
2
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
AVALANCHE LIMITING VALUE
SYMBOL
W
DSS
PARAMETER
Drain-source non-repetitive
unclamped inductive turn-off
energy
CONDITIONS
I
D
= 2.5 A; V
DD
≤
25 V;
V
GS
= 5 V; R
GS
= 50
Ω;
T
sp
= 25 ˚C
MIN.
-
TYP.
-
BUK9880-55
MAX.
30
UNIT
mJ
120
110
100
90
80
70
60
50
40
30
20
10
0
PD%
Normalised Power Derating
100
ID/A
RDS(ON) = VDS/ID
10
tp =
1 us
10us
100 us
1 ms
10ms
100ms
DC
1
0
20
40
60
80
100
Tmb / C
120
140
0.1
1
10
VDS/V
100
Fig.1. Normalised power dissipation.
PD% = 100
⋅
P
D
/P
D 25 ˚C
= f(T
sp
)
Fig.3. Safe operating area. T
sp
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Zth/ (K/W)
120
110
100
90
80
70
60
50
40
30
20
10
0
ID%
Normalised Current Derating
100
10
0.5
0.2
1
0.1
0.05
0.02
P
D
t
p
D=
t
p
T
t
0.1
T
0
20
40
60
80
Tmb / C
100
120
140
0.01
1.0E-06
0.0001
t/s
0.01
1
100
Fig.2. Normalised continuous drain current.
ID% = 100
⋅
I
D
/I
D 25 ˚C
= f(T
sp
); conditions: V
GS
≥
5 V
Fig.4. Transient thermal impedance.
Z
th j-sp
= f(t); parameter D = t
p
/T
April 1998
3
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
BUK9880-55
40
ID/A
30
VGS/V = 10
7
6
15
5.6
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2
4
VDS/V
6
8
10
14
gfs/S
13
12
11
10
9
8
7
6
5
0
5
10
ID/A
15
20
20
10
0
0
Fig.5. Typical output characteristics, T
j
= 25 ˚C.
I
D
= f(V
DS
); parameter V
GS
RDS(ON)/mOhm
Fig.8. Typical transconductance, T
j
= 25 ˚C.
g
fs
= f(I
D
); conditions: V
DS
= 25 V
115
110
105
100
95
90
85
2.5
a
BUK98XX-55
Rds(on) normalised to 25degC
4.2
4
4.4
4.6
4.8
5
2
1.5
1
80
75
70
5
10
15
20
25
0.5
-100
-50
0
ID/A
50
Tmb / degC
100
150
200
Fig.6. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(I
D
); parameter V
GS
20
ID/A
15
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
); I
D
= 5 A; V
GS
= 5 V
VGS(TO) / V
max.
2
typ.
1.5
BUK98xx-55
2.5
10
min.
1
5
Tj/C =
0
0
1
150
2
25
3
4
5
0.5
0
-100
-50
0
VGS/V
50
Tj / C
100
150
200
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
) ; conditions: V
DS
= 25 V; parameter T
j
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
April 1998
4
Rev 1.100
Philips Semiconductors
Product specification
TrenchMOS™ transistor
Logic level FET
BUK9880-55
1E-01
Sub-Threshold Conduction
40
IF/A
1E-02
2%
typ
98%
30
Tj/V =
20
150
25
1E-03
1E-04
10
1E-05
1E-05
0
0
0.5
1
1.5
2
2.5
3
0
0.5
1
VSDS/V
1.5
2
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C; V
DS
= V
GS
1
.9
.8
Thousands pF
.7
.6
.5
.4
.3
.2
.1
0
0.01
0.1
1
VDS/V
10
Coss
Crss
100
Ciss
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
WDSS%
120
110
100
90
80
70
60
50
40
30
20
10
0
20
40
60
80
100
Tmb / C
120
140
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
6
VDS/V
5
Fig.15. Normalised avalanche energy rating.
W
DSS
% = f(T
sp
); conditions: I
D
= 2.5 A
+
L
VDS = 14V
VDD
4
VDS = 44V
3
VDS
VGS
0
RGS
T.U.T.
R 01
shunt
-
-ID/100
2
1
0
0
2
4
6
QG/nC
8
10
12
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); conditions: I
D
= 7 A; parameter V
DS
Fig.16. Avalanche energy test circuit.
2
W
DSS
=
0.5
⋅
LI
D
⋅
BV
DSS
/(BV
DSS
−
V
DD
)
April 1998
5
Rev 1.100
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