Integrated
Circuit
Systems, Inc.
ICS2008B
SMPTE Time Code Receiver/Generator
General Description
The ICS2008B,
SMPTE Time Code Receiver / Generator
chip, is a VLSI device designed in a low power CMOS
process. This device provides the timing coordination for
Multimedia sight and sound events. Although it is aimed at
a PC Multimedia environment, the
ICS2008B
is easily
integrated into products requiring SMPTE time code
generation and/or reception in LTC (Longitudinal Time
Code) and/or VITC (Vertical Interval Time Code) formats
and MTC (MIDI Time Code) translation.
Taking its input from composite video, S-Video, or an
audio track, the
ICS2008B
can read SMPTE time code in
VITC and LTC formats. Time code output formats are LTC
and VITC. All are available simultaneously. A UART is
provided for the user to support MTC or tape transport
control.
The processor interface is compatible with the IBM PC and
ISA bus compatible computers and is easily interfaced to
other processors and micro-controllers.
The
ICS2008B
is an improved version of the
ICS2008,
with additional features and capabilities.
ICS2008 ICS2008B 2008 2008B
•
Features
•
•
•
•
•
Meets SMPTE VITC Specifications
Meets SMPTE and EBU LTC Specifications
Time Code Burn-in Window
– Programmable position, size and character attributes
LTC edge rate control
– Conforms to EBU T
r
and T
f
Specifications
Internal and external sync sources
– Genlock to video or house sync inputs
– Improved video timing lock during VCR pause and
shuttle modes
– Internally generated timing from oscillator input
– External click input
– Internal Timer
Allows 1/4 Frame MIDI Time Code Messages
LTC and VITC Generators
– Real Time SMPTE Rates:
30Hz, 29.97Hz, 25Hz, 24Hz
– Time Code Modes
Drop Frame and Color Frame
– VITC can be inserted on two lines from 10-40
(SMPTE specifies lines 10-20)
– Jam Sync, freewheeling, error bypass/correction,
and plus-one-frame capability
LTC Receiver
– Synchronize bit rates from 1/30
th
nominal to 80X
nominal playback speed.
VITC Receiver
– Reads code from any or all selected scan lines.
– VITC search mode, will search through VBI lines until
VITC is found.
New UART frequency of 38.4 K for tape transport control
Block Diagram
•
•
•
ICS2008B Rev D 4/05/05
ICS reserves the right to make changes in the device data identified in this publication without
further notice. ICS advises its customers to obtain the latest version of all device data to verify
that any information being relied upon by the customer is current and accurate.
ICS2008B
Package Pinouts
LTCIN+
LTCIN-
CLICK
FRAME
RESET
INTR
D7
6 5 4 3 2
LTCOUT
LFC
XTAL2
XTAL1
AVDD
AVSS
COUT
YOUT
C2
Y2
C1
7
8
9
10
11
12
13
14
15
16
17
1
44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
D2
D1
D0
IOW*
VDD
VSS
IOR*
UARTCS*
SMPTECS*
A1
A0
18 19 20 21 22 23 24 25 26 27 28
Y1
STHRESH
CTHRESH
DTHRESH
RXD
CTS*
TXD
D6
D5
D4
D3
D2
D1
D0
IOW*
VDD
VSS
IOR*
UARTCS*
SMPTECS*
A1
A0
RTS*
LRCLK
VITCGATE
VITCOUT
2
LTCOUT
LFC
XTAL2
XTAL1
AVDD
AVSS
COUT
YOUT
C2
Y2
C1
44 43 42 41 40 39 38 37 36 35 34
1
33
2
32
31
3
4
30
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
Y1
STHRESH
CTHRESH
DTHRESH
RXD
CTS*
TXD
ICS2008B Rev D 4/05/05
LTCIN+
LTCIN-
CLICK
FRAME
RESET
INTR
D7
RTS*
LRCLK
VITCGATE
VITCOUT
D6
D5
D4
D3
ICS2008B
Pin Descriptions
PIN NUMBER
TQFP PLCC
12, 10
11, 9
15
13
14
8
7
41
42
44
43
1
20
22
21
18
16
17
19
4
3
2
24, 23
27
30
25
26
40
38–31
39
5
6
29
28
18, 16
17, 15
PIN
NAME
Y1, Y2
C1, C2
TYPE
AI
AI
AI
AI
AI
AO
AO
AI
AI
AI
AI
AO
O
O
O
O
I
I
O
I
O
AI
I
I
I
I
I
I
I/O
O
P
P
P
P
DESC RIPTI ON
Video inputs from camera or other source. NOTE: This is also the Y
(Luma) input for S-VHS and HI-8 systems.
C (Chroma) inputs for S-VHS and HI-8 systems. In NTSC systems, this
pin should be tied to its respective Y input.
Data Threshold bypass input.
SYNC Threshold bypass input.
Clamp Threshold bypass input.
Video output. This is also the Y (Luma) output in S-Video mode.
C (Chroma) output for S-VHS and HI-8 systems.
Color Frame A/B input. This input is self biased (See Applications).
LTC SYNC input. This input is self biased (See Applications).
SMPTE LTC input+. This input is self biased (See Applications).
SMPTE LTC input–. This input is self biased (See Applications).
SMPTE LTC output
SMPTE LTC receive clock output.
SMPTE VITC output to video mixer circuit.
VITC gate indicates VITC code is being output for video overlay.
UART Transmit data
UART Receive data
Clear to Send
Ready to Send
14.318 MHz crystal input.
14.318 MHz crystal oscillator output.
Tie to +5 VDC
Address bus
Read Enable (active low)
Write Enable (active low)
SMPTE port chip select (active low)
UART chip select (active low)
Master reset (active high)
Bi-directional data bus
Interrupt Request (active high)
Analog V
DD
Analog Ground
Digital V
DD
Digital
21
DTHRESH
19
STHRESH
20
CTHRESH
14
Y OUT
13
C OUT
3
FRAME
4
CLICK
6
LTCIN+
5
LTCIN–
7
LTCOUT
26
LRCLK
28
VITCOUT
27
VITCGATE
24
TxD
22
RxD
23
CTS*
25
RTS*
10
XTAL1
9
XTAL2
8
LFC
30, 29 A1-A0
33
IOR*
36
IOW*
31
SMPTECS*
32
UARTCS*
2
RESET
44–37 D7-D0
1
INTR
11
AVDD
12
AVSS
35
VDD
34
VSS
TYPE:
A – Analog • P – Power • I – Input • O – Output
2008 2008B ICS2008
3
ICS2008B Rev D 4/05/05
ICS2008B
Functional Description
The following is a functional description of the hardware regis-
ters in the
ICS2008B
chip. It also describes how those
registers can be utilized by the software to facilitate specific
application services.
Video Output
The video output combines the selected video input with the
outputs from the VITC generator and the character generator.
It can be a composite or an S-Video output as selected by the
SVID bit in the SMPTE control registers.
VITC code is generated from data in the VITC generator
buffer and output during the selected line time(s). The CRC
and synchronizing bits are automatically generated by the
VITC generator, but all of the data fields are sent directly from
the buffer with no modification.
A character generator is provided to insert the time code in a
burn-in window which overlays the incoming video. The ver-
tical and horizontal position of the burn-in window is
programmable.
Hardware Environments
The
ICS2008B
operates as a peripheral to a processor such as
a PC or a single chip microprocessor. Many of the real time
requirements are satisfied by double buffering both incoming
and outgoing time codes.
LTC Input
LTCIN is a differential analog input feeding a comparator
with hysteresis. It requires capacitive coupling to the LTC
source. The output of the comparator goes to the LTC re-
ceiver, which is capable of receiving LTC in a forward or
backward direction at a rate from 1/30
th
to 80X nominal
frame rates. The incoming LTC data is sampled with a phase-
locked clock and loaded into the receive buffer following the
receipt of a valid LTC SYNC pattern. When a complete frame
has been received, an interrupt is generated.
SMPTE SYNC Sources
A time code generator must have a SYNC input from a stable
source in order to position the LTC code properly on a audio
track of video tape or film. Three SYNC sources, video, click
input, and free running, are available. In the case of a video
tape, LTC code must start within plus or minus one line of the
beginning of line 5. This requires “Genlocking” to the incom-
ing video. The video timing section locks to the video’s
horizontal and vertical SYNC signal and generates a SMPTE
SYNC. If some external SYNC source is available it can be
input on the CLICK input. Otherwise, a free running SMPTE
SYNC is generated from the oscillator at the selected frame
rate.
LTC Output
The LTC output can be analog or digital. When set up as an
analog output, it can drive a high impedance load.
The LTC generator outputs a LTC frame at the selected frame
rate, such as 24 Hz, 25 Hz, 29.97 Hz or 30 Hz, and starts the
frame based on a start time generated by the selected LTC
SYNC source.
The output edge rate is programmable for SMPTE code (25
µsec)
and EBU code (50
µsec)
rise and fall times.
Video Timing Generator
The video timing generator is “Genlocked” to the video
input’s SYNC separator. It extracts NTSC or PAL timing in-
formation from the video input and generates line and pixel
rate timing for the VITC receiver, VITC generator, LTC gen-
erator and character generator. If no video input is present, it
generates free running timing.
Video Inputs
There are two sets of video inputs. In a composite NTSC or
PAL system, the Y input is the only one used. It is capacitively
coupled to the source. In S-Video systems, capacitively couple
Y and C to their respective sources. Proper termination of the
source should be observed. Unused inputs may be left open.
One of the two video sources is selected by the VIDSEL bit in
the SMPTE control registers as the video SYNC source. Inter-
nal timers are synchronized with the incoming video to extract
timing information used to receive and generate VITC.
The VITC receiver samples the incoming video looking for a
valid VITC code on selected scan lines. When a valid code is
received it is written to a VITC receive buffer. More than one
line can contain VITC code, and the codes can be different. For
this reason, VITC codes from selected lines of a frame are writ-
ten to separate VITC buffers.
Overlay Character Generator
It is sometimes desirable to display the time code on a video
display along with the picture. A character generator is pro-
vided for that purpose. The time code display, or burn-in
window, can be positioned anywhere on the screen. It can be
displayed in two sizes with white or black characters on a
black, white or live video background.
ICS2008B Rev D 4/05/05
4
ICS2008B
UART
A general purpose UART is provided for MIDI, video trans-
port control, etc. Most serial interface transport controls use
9600 and 38.4K BAUD. The CTS and RTS modem controls are
needed in these applications. MIDI ports use 31.25K BAUD,
but they do not require modem controls. The receiver includes
a four byte FIFO to reduce the real time interrupt servicing re-
quirements. This is particularly important in MIDI applications
because of the high data rate and the fact that many MIDI mes-
sages are three bytes long. The transmitter is doubled
buffered. Interrupts can be generated on both
receiver data available and/or transmit buffer empty.
LRI, LXI, VLI and TMI reflect the status of the potential
interrupt sources to the processor. When a bit is set to one and
the corresponding enable bit, LRIEN, LXIEN or VLIEN, is also
set, the INTR output will be activated. Interrupts are cleared by
reading SMPTE0.
7
6
5
4
3
2
1
0
SMPTE0
Interrupt Control/Status
LRI (LTC RCV Interrupt)
LXI (LTC XMT Interrupt)
VLI (Video Line Interrupt)
LRIEN (1-enable, 0-disable)
LXIEN (1-enable, 0-disable)
VLIEN (1-enable, 0-disable)
TMI (Timer Interrupt)
TMIEN (1-enable, 0-disable)
Interrupt Timer
The interrupt timer is a general purpose 10 bit timer with three
clock sources (100 kHz, the LTC receive clock and the LTC
transmit clock). Although the timer is general purpose in
nature, its main purpose is to facilitate the timed generation of
MIDI time code messages.
Processor Interface
The
ICS2008B
supports standard microprocessor interfaces
and busses, such as the PC bus, to allow access to six control/
status and data registers. These six registers are organized into
two groups, one set of four for SMPTE control and the other
set of two for direct UART port control. Each set of registers is
selected with its own chip select, SMPTECS* and UARTCS.*
LRI —
This bit indicates that a LTC receive interrupt has
occurred. In order for an actual processor interrupt to occur,
the LRIEN bit must also be set. An LRI interrupt occurs upon
reception of the last byte of LTC receive data which was pre-
ceded by a valid LTC SYNC pattern. That is after the 64
th
LTC receive bit time in the forward direction. At normal
frame rates, if the LTC transmitter is synchronized with the
LTC receiver, there is about 3 milliseconds after this interrupt
before the LTC transmit data for the next output frame is
transferred to the output buffer.
LXI —
This bit indicates that a LTC transmit interrupt has
occurred. When this bit is set, and the corresponding LXIEN
bit has been set, the INTR output will be activated. The LTC
transmit interrupt is activated after the transfer of LTC trans-
mit data to the output buffer. This occurs after LTXEN is set to
one and after the 72
nd
LTC transmits bit time of the current
frame, “N.” Data loaded after this interrupt will appear in out-
put frame “N+2” since the transmitter is double buffered.
VLI —
This is a status bit that indicates that the video line
selected via the Video Interrupt Line Register, VR9, has
passed. When the VLIEN bit is also set, the processor will be
interrupted. This interrupt can be used by the processor to
determine when to sample the VITC time code when time
locked to a video source. It will also be used to facilitate
detection of LTC time code dropout and off speed LTC code,
e.g. shuttling operations.
TMI —
This bit indicates that a timer interrupt has occurred.
When the TMIEN bit is also set to a one, the INTR output will
be activated. This interrupt is intended to facilitate timing
MIDI clocks and MIDI Quarter Frame messages.
SMPTE Registers
The SMPTE register set allows access to four direct and
64 indirect registers. The first two direct access registers
addressed at locations 0 and 1 are for status and interrupt con-
trol. The 64 indirect registers are accessed by writing an
indirect address into SMPTE2 and reading from or writing to
SMPTE3. If the AUTOINC bit in SMPTE2 is set to 1, the
indirect register address is automatically incremented after an
access to SMPTE3. This eases the task of reading or writing
sequential indirect locations.
S M P TE C S *
0
0
0
0
A1
A1
0
0
1
1
A0
A0
0
1
0
1
R E G IS T E R
r / au
S M P TE 0 -I t ruptC ontolS t t s
ner
S M P T E 1 -S M P T E S t t s
au
S M P TE 2 -I diectA ddr ss R egi t r
n r
e
se
S M P TE 3 -I diectR egi t rD at
n r
se
a
The SMPTE0 Register contains the SMPTE interrupt controls
and status and the VITC read status. The four interrupt bits,
5
ICS2008B Rev D 4/05/05
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