EEWORLDEEWORLDEEWORLD

Part Number

Search

3GDF14-F-80N-FREQ

Description
LVDS Output Clock Oscillator, 38MHz Min, 640MHz Max, DIP-14/4
CategoryPassive components    oscillator   
File Size114KB,1 Pages
ManufacturerEuroquartz
Websitehttp://www.euroquartz.co.uk/
Download Datasheet Parametric View All

3GDF14-F-80N-FREQ Overview

LVDS Output Clock Oscillator, 38MHz Min, 640MHz Max, DIP-14/4

3GDF14-F-80N-FREQ Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerEuroquartz
Reach Compliance Codecompliant
Maximum control voltage3 V
Minimum control voltage0.3 V
maximum descent time0.7 ns
Frequency Adjustment - MechanicalNO
Frequency offset/pull rate80 ppm
frequency stability100%
Installation featuresTHROUGH HOLE MOUNT
Maximum operating frequency640 MHz
Minimum operating frequency38 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeLVDS
Output load50 OHM
physical size20.2mm x 12.8mm x 5.08mm
longest rise time0.7 ns
Maximum supply voltage3.465 V
Minimum supply voltage3.135 V
Nominal supply voltage3.3 V
surface mountNO
maximum symmetry55/45 %
Base Number Matches1
EURO
QUARTZ
14 pin Dual-in-Line
Frequency range 38MHz to 640MHz
LVDS Output
Supply Voltage 3.3 VDC
Phase jitter 0.4ps typical
Pull range from ±30ppm to ±150ppm
GDF14 LVDS VCXO
38.0MHz to 640.0MHz
OUTLINE & DIMENSIONS
DESCRIPTION
GDF14 VCXOs are packaged in an industry-standard 14 pin dual-in-
line package. Typical phase jitter for GDF series VCXOs is 0.4 ps.
Output is LVDS. Applications include phase lock loop, SONET/ATM,
set-top boxes, MPEG , audio/video modulation, video game consoles
and HDTV.
SPECIFICATION
Frequency Range:
Supply Voltage:
Output Logic:
RMS Period Jitter:
Peak to Peak Jitter:
Phase Jitter:
Initial Frequency Accuracy:
Output Voltage HIGH (1):
Output Voltage LOW (0):
Pulling Range:
Control Voltage Range:
Temperature Stability:
Output Load:
Rise/Fall Times:
Duty Cycle:
Start-up Time:
Current Consumption:
Static Discharge Protection:
Storage Temperature:
Ageing:
Enable/Disable:
RoHS Status:
38.0MHz to 640.0MHz
3.3 VDC ±5%
LVDS
3.0ps typical
20.0ps typical, 30.0ps maximum
0.4ps typical, 5.0ps maximum
Tune to the nominal frequency
with Vc= 1.65 ±0.2VDC
1.4 Volts typical
1.1 Volts typical
From ±30ppm to ±150ppm
1.65 ±1.35 Volts
See table
50W into Vdd or Thevenin equiv.
0.5ns typ., 0.7ns max.
20% Vdd to 80% Vdd
50% ±5%
(Measured at Vdd-1.3V)
10ms maximum, 5ms typical
55mA typical, 60mA maximum
(At 202.50MHz)
2kV maximum
-55° to +150°C
±2ppm per year maximum
Not implemented - 4 pin package
Fully compliant or non compliant
PART NUMBERING
Example:
3GPF14G-B-80N-60.000
Supply Voltage
3 = +3.3V
Series Designator
GDF14
RoHS Status
G = RoHs compliant
Blank = RoHS non-compliant
Stability over temperature range
(See table)
Pullability in ±ppm
Pullability determinator
N = minimum
M = maximum
T = Typical
Frequency in MHz
FREQUENCY STABILITY
Stability Code Stability ±ppm Temp. Range
A
25
0°~+70°C
B
50
0°~+70°C
C
100
0°~+70°C
D
25
-40°~+85°C
E
50
-40°~+85°C
F
100
-40°~+85°C
If non-standard frequency stability is required
Use ‘I’ followed by stability, i.e. I20 for ±20ppm
EUROQUARTZ LIMITED Blacknell Lane CREWKERNE Somerset UK TA18 7HE
Tel: +44 (0)1460 230000 Fax: +44 (0)1460 230001 info@euroquartz.co.uk www.euroquartz.co.uk
Please take a look at my error message (VHDL register group)
编译reg_aggr.vhd总是出现这个错误 Error:Termination notification:errors in ...eg_aggr.vhd prevent from further processing------------------------------------------reg_aggr.vhd------------------------------------...
villaining Embedded System
Half-bridge LC resonance principle
Half-bridge LC resonance principle...
hemingjun991 Analog electronics
64 keys
[i=s]This post was last edited by paulhyde on 2014-9-15 09:13[/i] 64 keys...
tmstd Electronics Design Contest
About C6678 using SPI to start multi-core
Platform: C6678 We use a board made by another company. The current situation is that without adding SYS/BIOS, we can complete the multi-core startup through SPI. For example, add the acquisition of c...
guzl86 DSP and ARM Processors
I'd like to ask if anyone uses PB5 under Vista.
There seems to be an incompatibility issue....
ydq850524 Embedded System
Design of motor drive circuit
Sincerely provide it to those who need help, free of charge...
Yound Electronics Design Contest

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2468  565  489  1302  1314  50  12  10  27  4 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号