MC9S12DJ64CFUE datasheet, PDF - EEWORLD Datasheet

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MC9S12DJ64CFUE: Description16-BIT, FLASH, 25MHz, MICROCONTROLLER, PQFP80, PLASTIC, QFP-80; CategoryThe embedded processor and controller Microcontrollers and processors; File Size615KB，128 Pages; ManufacturerFREESCALE (NXP); Environmental Compliance

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MC9S12DJ64CFUE Overview

16-BIT, FLASH, 25MHz, MICROCONTROLLER, PQFP80, PLASTIC, QFP-80

MC9S12DJ64CFUE Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Objectid	2069912457
Parts packaging code	QFP
package instruction	PLASTIC, QFP-80
Contacts	80
Reach Compliance Code	compliant
ECCN code	3A991.A.2
Samacsys Description	Multi-Core Audio Processors
Samacsys Manufacturer	NXP
Samacsys Modified On	2023-03-07 16:10:32
Has ADC	YES
Other features	ALSO REQUIRES 5V SUPPLY
Address bus width	16
bit size	16
CPU series	CPU12
maximum clock frequency	16 MHz
DAC channel	NO
DMA channel	NO
External data bus width	16
JESD-30 code	S-PQFP-G80
JESD-609 code	e3
length	14 mm
Humidity sensitivity level	3
Number of I/O lines	59
Number of terminals	80
On-chip program ROM width	8
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP80,.68SQ
Package shape	SQUARE
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
RAM (bytes)	4096
rom(word)	65536
ROM programmability	FLASH
Maximum seat height	2.45 mm
speed	25 MHz
Maximum slew rate	50 mA
Maximum supply voltage	2.75 V
Minimum supply voltage	2.35 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	14 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER

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DOCUMENT NUMBER

9S12DJ64DGV1/D

MC9S12DJ64

Device User Guide

V01.20

Covers also

MC9S12D64, MC9S12A64, MC9S12D32,

MC9S12A32

Original Release Date: 19 Nov. 2001

Revised: 6 April 2005

Freescale Semiconductor,

Inc.

Freescale

reserves the right to make changes without further notice to any products herein to improve reliability, function or

design.

Freescale

does not assume any liability arising out of the application or use of any product or circuit described herein;

neither does it convey any license under its patent rights nor the rights of others.

Freescale

products are not designed, intended,

or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to

support or sustain life, or for any other application in which the failure of the

Freescale

product could create a situation where

personal injury or death may occur. Should Buyer purchase or use

Freescale

products for any such unintended or unauthorized

application, Buyer shall indemnify and hold

Freescale

and its officers, employees, subsidiaries, affiliates, and distributors harmless

against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of

personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that

Freescale

was

negligent regarding the design or manufacture of the part.

MC9S12DJ64 Device User Guide — V01.20

Table of Contents

Section 1 Introduction

1.1

1.2

1.3

1.4

1.5

1.5.1

1.6

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Section 2 Signal Description

2.1

Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

2.2

Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

2.3

Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

2.3.1

EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

2.3.2

RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

2.3.3

TEST — Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

2.3.4

VREGEN — Voltage Regulator Enable Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

2.3.5

XFC — PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

2.3.6

BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin . . . . . . . .56

2.3.7

PAD15 / AN15 / ETRIG1 — Port AD Input Pin of ATD1 . . . . . . . . . . . . . . . . . . . . . .57

2.3.8

PAD[14:08] / AN[14:08] — Port AD Input Pins ATD1 . . . . . . . . . . . . . . . . . . . . . . . .57

2.3.9

PAD07 / AN07 / ETRIG0 — Port AD Input Pin of ATD0 . . . . . . . . . . . . . . . . . . . . . .57

2.3.10 PAD[06:00] / AN[06:00] — Port AD Input Pins of ATD0 . . . . . . . . . . . . . . . . . . . . . .57

2.3.11 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins . . . . . . . . . . . . . . . . . . . . . . .57

2.3.12 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . .57

2.3.13 PE7 / NOACC / XCLKS — Port E I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

2.3.14 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

2.3.15 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

2.3.16 PE4 / ECLK — Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

2.3.17 PE3 / LSTRB / TAGLO — Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

2.3.18 PE2 / R/W — Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

2.3.19 PE1 / IRQ — Port E Input Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

2.3.20 PE0 / XIRQ — Port E Input Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

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