DOCUMENT NUMBER
9S12DJ64DGV1/D
MC9S12DJ64
Device User Guide
V01.20
Covers also
MC9S12D64, MC9S12A64, MC9S12D32,
MC9S12A32
Original Release Date: 19 Nov. 2001
Revised: 6 April 2005
Freescale Semiconductor,
Inc.
Freescale
reserves the right to make changes without further notice to any products herein to improve reliability, function or
design.
Freescale
does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent rights nor the rights of others.
Freescale
products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the
Freescale
product could create a situation where
personal injury or death may occur. Should Buyer purchase or use
Freescale
products for any such unintended or unauthorized
application, Buyer shall indemnify and hold
Freescale
and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Freescale
was
negligent regarding the design or manufacture of the part.
1
Revision History
Version Revision Effective
Number
Date
Date
V01.00
16 NOV
2001
18 FEB
2002
19 NOV
2001
18 FEB
2002
Author
Description of Changes
Initial version based on MC9SDP256-2.09 Version.
In table 7 I/O Characteristics" of the electrical characteristics
replaced tPULSE with tpign and tpval in lines "Port ... Interrupt Input
Pulse filtered" and "Port ... Interrupt Input Pulse passed"
respectively.
Table "Oscillator Characteristics": removed "Oscillator start-up time
from POR or STOP" row
Table "5V I/O Characteristics": Updated
Partial Drive IOH = +–2mA and Full Drive IOH = –10mA
Table "ATD Operating Characteristics": Distinguish I
REF
for 1 and 2
ATD blocks on
Table "ATD Electrical Characteristics": Update C
INS
to 22 pF
Table "Operating Conditions": Changed V
DD
and V
DDPLL
to 2.35 V
(min)
Removed Document number except from Cover Sheet
Updated Table "Document References"
Table "5V I/O Characteristics" : Corrected Input Capacitance to 6pF
Section: "Device Pinout" (112-pin and 80-pin): added in diagrams
RXCAN0 to PJ6 and TXCAN0 to PJ7
Table "PLL Characteristics": Updated parameters K
1
and f
1
Figure "Basic PLL functional diagram": Inserted XFC pin in diagram
Enhanced section "XFC Component Selection"
Added to Sections ATD, ECT and PWM: freeze mode = active BDM
mode
Added 1L86D to Table "Assigned Part ID numbers"
Corrected MEMSIZ1 value in Table "Memory size registers"
Subsection "Device Memory Map: Removed Flash mapping from
$0000 to $3FFF.
Table "Signal Properties": Added column "Internal Pull Resistor".
Preface Table "Document References": Changed to full naming for
each block.
Table "Interrupt Vector Locations", Column "Local Enable":
Corrected several register and bit names.
Figure "Recommended PCB Layout for 80QFP: Corrected
VREGEN pin position
Thermal values for junction to board and package
BGND pin pull-up
Part Order Information
Global Register Table
Chip Configuration Summary
Modified mode of Operations chapter
Section "Printed Circuit Board Layout Proposals": added Pierce
Oscillator examples for 112LQFP and 80QFP
V01.01
V01.02
6 MAR
2002
6 MAR
2002
V01.03
4 June
2002
4 June
2002
V01.04
4 July
2002
4 July
2002
V01.05
30 July
2002
30 July
2002
MC9S12DJ64 Device User Guide — V01.20
Version Revision Effective
Number
Date
Date
V01.06
20 Aug.
2002
20 Aug.
2002
Author
Description of Changes
NVM electricals updated
Subsection "Detailed Register Map: Address corrections
Preface, Table "Document references": added OSC User Guide
New section "Oscillator (OSC) Block Description"
Electrical Characteristics:
-> Section "General": removed preliminary disclaimer
->Table "Supply Current Characteristics":
changed max Run IDD from 65mA to 50mA
changes max Wait IDD from 40mA to 30mA
changed max Stop IDD from 50uA to 100uA
Section HCS12 Core Block Description: mentioned alternate clock
of BDM to be equivalent to oscillator clock
Table "5V I/O Characteristics": Corrected Input Leakage Current to
+/- 1 uA
Section "Part ID assignment": Located on start of next page for
better readability
Added MC9S12A64 derivative to cover sheet and "Derivative
Differences" Table
Corrected in footnote of Table "PLL Characteristics": f
OSC
= 4MHz
Renamed "Preface" section to "Derivative Differences and
Document references". Added details for derivatives missing CAN0
and/or BDLC
Table "ESD and Latch-up Test Conditions": changed pulse numbers
from 3 to 1
Table "ESD and Latch-Up Protection Characteristics": changed
parameter classification from C to T
Table "5V I/O Characteristics": removed foot note from "Input
Leakage Current"
Table " Supply Current Characteristics": updated Stop and Pseudo
Stop currents
Subsection "Detailed Register Map": Corrected several entries
Subsection "Unsecuring the Microcontroller": Added more details
Table "Operating Conditions": improved footnote 1 wording, applied
footnote 1 to PLL Supply Voltage.
Tables "SPI Master/Slave Mode Timing Characteristics: Corrected
Operating Frequency
Appendix ’NVM, Flash and EEPROM’: Replaced ’burst
programming’ by ’row programming
Table "Operating Conditions": corrected minimum bus frequency to
0.25MHz
Section "Feature List": ECT features changed to "Four pulse
accumulators ..."
Replaced references to HCS12 Core Guide by the individual
HCS12 Block guides
Table "Signal Properties" corrected pull resistor reset state for PE7
and PE4-PE2.
Table "Absolute Maximum Ratings" corrected footnote on clamp of
TEST pin.
Added cycle definition to "CPU 12 Block Description".
Added register reset values to MMC and MEBI block descriptions.
Diagram "Clock Connections": Connect Bus Clock to HCS12 Core
V01.07
20 Sept.
2002
20 Sept.
2002
V01.08
25 Sept.
2002
25 Sept.
2002
V01.09
10 Oct.
2002
10 Oct.
2002
V01.10
8 Nov.
2002
8 Nov.
2002
V01.11
24 Jan.
2003
24 Jan.
2003
V01.12
31 Mar.
2003
31 Mar.
2003
V01.13
20 May
2003
20 May
2003
V01.14
10 June
2003
10 June
2003
3
MC9S12DJ64 Device User Guide — V01.20
Version Revision Effective
Number
Date
Date
V01.15
V01.16
V01.17
V01.18
V01.19
22 July
2003
24 Feb.
2004
21 May
2004
13 July
2004
2 Sept.
2004
6 April
2005
22 July
2003
24 Feb.
2004
21 May
2004
13 July
2004
2 Sept.
2004
6 April
2005
Author
Description of Changes
Mentioned "S12 LRAE" bootloader in Flash section
Section Document References: corrected S12 CPU document
reference
Added 3L86D maskset with corresponding Part ID
Table Oscillator Characteristics: Added more details for EXTAL pin
Added 4L86D maskset with corresponding Part ID
Table "MC9S12DJ64 Memory Map out of Reset": corrected $1000 -
$3fff memory in single chip modes to "unimplemented".
Added MC9S12D32 and MC9S12A32
Appendix, Table "Oscillator Characteristics": changed
item 13 VIH,EXTAL min value from 0.7*VDDPLL to 0.75*VDDPLL
item 14 VIL,EXTAL max value from 0.3*VDDPLL to 0.25*VDDPLL
Table "Assigned Part ID Numbers": added mask set number
0M89C
Table "NVM Reliability Characteristics": added footnote concerning
data retention
V01.20
4
MC9S12DJ64 Device User Guide — V01.20
Table of Contents
Section 1 Introduction
1.1
1.2
1.3
1.4
1.5
1.5.1
1.6
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Section 2 Signal Description
2.1
Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
2.2
Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
2.3
Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
2.3.1
EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
2.3.2
RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
2.3.3
TEST — Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
2.3.4
VREGEN — Voltage Regulator Enable Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
2.3.5
XFC — PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
2.3.6
BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin . . . . . . . .56
2.3.7
PAD15 / AN15 / ETRIG1 — Port AD Input Pin of ATD1 . . . . . . . . . . . . . . . . . . . . . .57
2.3.8
PAD[14:08] / AN[14:08] — Port AD Input Pins ATD1 . . . . . . . . . . . . . . . . . . . . . . . .57
2.3.9
PAD07 / AN07 / ETRIG0 — Port AD Input Pin of ATD0 . . . . . . . . . . . . . . . . . . . . . .57
2.3.10 PAD[06:00] / AN[06:00] — Port AD Input Pins of ATD0 . . . . . . . . . . . . . . . . . . . . . .57
2.3.11 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins . . . . . . . . . . . . . . . . . . . . . . .57
2.3.12 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . .57
2.3.13 PE7 / NOACC / XCLKS — Port E I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
2.3.14 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.15 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.16 PE4 / ECLK — Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.17 PE3 / LSTRB / TAGLO — Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.18 PE2 / R/W — Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.19 PE1 / IRQ — Port E Input Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
2.3.20 PE0 / XIRQ — Port E Input Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
5
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