QorIQ Communications Platforms
P Series
QorIQ P1011 and P1020
communications processors
Overview
Freescale QorIQ communications platforms are
the next-generation evolution of our leading
PowerQUICC communications processors. Built
using high-performance Power Architecture
®
cores, QorIQ platforms enable a new era of
networking innovation where the reliability,
security and quality of service for every
connection matters.
The P1011 and P1020 processors are ideally
suited for multiservice gateways, Ethernet switch
controllers, wireless LAN access points and high-
performance general-purpose control processor
applications with tight thermal constraints.
The P1011 and P1020 processors are
pin-compatible with the QorIQ P2 platform
products, offering a four-chip range of cost-
effective solutions. Scaling from a single core
at 533 MHz (P1011) to a dual core at
1.2 GHz per core (P2020), the combined
QorIQ platforms offer an impressive 4.5x
aggregate frequency range.
The P1011 and P1020 platforms are software
compatible, and both feature the e500 Power
Architecture core and peripherals, as well
as being fully software compatible with the
earlier PowerQUICC processors. This enables
customers to create a product with multiple
performance points from a single board design.
The P1020 dual-core processor supports both
symmetric and asymmetric processing, enabling
customers to further optimize their design with
the same applications running on each core
or serialize their application using the cores for
different processing tasks.
QorIQ P1011 and P1020
Communications Processors
The QorIQ P1 family, which includes the P1011
and P1020 communications processors, offers
the value of smart integration and efficient
power for a wide variety of applications in the
networking, telecom, defense and industrial
markets. Based on 45 nm technology for low
power, the P1011 and P1020 processors provide
both single- and dual-core options, from
533–800 MHz, along with advanced security
and a rich set of interfaces.
QorIQ P1020 and P1011 Block Diagram
QorIQ P1011 and P1020 Block Diagram
Not on P1011
Security
Acceleration
XOR
Power Architecture
®
e500 Core
32 KB
32 KB
L1 I Cache L1 D Cache
Power Architecture
e500 Core
32 KB
32 KB
L1 I Cache L1 D Cache
DDR2/DDR3
SDRAM Controller
256 KB
L2 Cache
DUART, 2x I
2
C, Timers,
Interrupt Control,
SD/MMC, SPI,
2x USB 2.0/ULPI
Coherency Module
System Bus
Enhanced Local Bus
Controller (eLBC)
TDM
3x
Gigabit
Ethernet
On-Chip Network
2x PCI Express
®
4-ch. DMA Controller
4-lane SerDes
Core Complex (CPU, L2 and Frontside CoreNet Platform Cache)
Accelerators and Memory Control
Networking Elements
Basic Peripherals and Interconnect
The P1011 and P1020 processors have an
advanced set of features for ease of use. The
256 KB L2 cache offers incremental configuration
to partition the cache between the two cores or
to configure it as SRAM or stashing memory.
The integrated security engine supports the
cryptographic algorithms commonly used
in IPsec, SSL, 3GPP and other networking
and wireless security protocols. The memory
controller offers future-proofing against memory
technology migration with support for both DDR2
and DDR3. It also supports error correction
codes, a baseline requirement for any high-
reliability system.
The P1011 and P1020 processors integrate
a rich set of interfaces, including a 4-lane
multiprotocol SerDes, Gigabit Ethernet, PCI
Express
®
and USB. The three 10/100/1000
Ethernet ports support advanced packet parsing,
flow control and quality of service features, as
well as IEEE
®
1588 time-stamping—all ideal for
managing the datapath traffic between the LAN
and WAN interface. A TDM interface can support
voice for legacy phone applications. Four SerDes
lanes can be portioned across two PCI Express
ports and two SGMII ports. The PCI Express
ports can provide connectivity to IEEE 802.11n
radio cards for wireless support. USB or SD/
MMC interfaces can be used to support local
storage. A second USB interface is also available
to support USB attached printers or as a console
port. Multiple memory connection ports are
available, including the 16-bit local bus, two USB
2.0 controllers, eSDHC and SPI.
available junction temperature range of –40 ºC
to +125 ºC, the devices can be used in power-
sensitive defense and industrial applications,
and outdoor environments less protected from
the environment. The devices’ primary
target applications are networking and
telecom linecards.
A multiservice router or business gateway
requires a combination of high performance
and a rich set of peripherals to support the
datapath throughputs and required system
functionality. The P1011 and P1020 devices
offer a scalable platform to develop a range of
products that can support the same feature set.
Integrated 10/100/1000 Ethernet controllers
with classification and QoS capabilities are ideal
for managing the datapath traffic between the
LAN and WAN interface. PCI Express ports
can provide connectivity to IEEE 802.11n radio
cards for wireless support, TDM for legacy
phone interfaces to support voice and the USB
or SD/MMC interfaces can be used to support
local storage. The second USB interface is
also available to support USB-attached printers
or as a console port. And the integrated
security engine can provide encrypted secure
communications for remote users with
VPN support.
• Three 10/100/1000 Mb/s enhanced three-
speed Ethernet controllers (eTSECs)
TCP/IP acceleration and
classification capabilities
IEEE 1588 support
Lossless flow control
RGMII, SGMII
• High-speed interfaces (not all
available simultaneously)
Four SerDes to 3.125 GHz multiplexed
across controllers
Two PCI Express controllers
Two SGMII interfaces
• Two High-Speed USB controllers (USB 2.0)
Host and device support
Enhanced host controller interface (EHCI)
ULPI interface to PHY
• Enhanced secure digital host controller
(eSDHC)
• Serial peripheral interface
• Integrated security engine (SEC 3.3)
Crypto algorithm support includes 3DES,
AES, RSA/ECC, MD5/SHA, ARC4, Snow
3G and FIPS deterministic RNG
Single pass encryption/message
authentication for common security
protocols (e.g., IPsec, SSL, SRTP, WiMAX)
XOR acceleration
• 32-bit DDR2/DDR3 SDRAM memory
controller with ECC support
• Programmable interrupt controller (PIC)
compliant with OpenPIC standard
• Four-channel DMA controller
• Two I
2
C controllers, DUART, timers
• Enhanced local bus controller (eLBC)
• 16 general-purpose I/O signals
• Package: 689-pin wirebond power-BGA
(TEPBGA2)
Technical Specifications
• Dual (P1020) or single (P1011) high-
performance Power Architecture e500 cores
36-bit physical addressing
Double-precision floating-point support
32 KB L1 instruction cache and 32 KB L1
data cache for each core
533–800 MHz core
clock frequency
• 256 KB L2 cache with ECC, also
configurable as SRAM and stashing memory
Target Applications
The P1011 and P1020 processors serve in
a wide variety of applications. The devices
are well suited for various combinations of
data plane and control plane workloads in
networking and telecom applications. With an
QorIQ P1020 and P1011 Features
QorIQ
Platform
P1
P1
P2
P2
Device
P1011
P1020
P2010
P2020
Cores
1
2
1
2
Top Core
Frequency
800 MHz
800 MHz
1200 MHz
1200 MHz
L2 Size
256
256
512
512
KB
KB
KB
KB
DDR 2/3 Support GE Ports
32-bit
32-bit
64-bit
64-bit
with
with
with
with
ECC
ECC
ECC
ECC
3
3
3
3
QUICC
Engine
4
4
4
4
SerDes
2
2
3
3
PCI Express
N/A
N/A
2
2
Serial RapidIO
Yes
Yes
N/A
N/A
TDM
Yes
Yes
In QUICC Engine
In QUICC Engine
For more information, please visit
freescale.com/QorIQ
Freescale, the Freescale logo, PowerQUICC and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.
QUICC Engine and CoreNet are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of
their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks
are trademarks and service marks licensed by Power.org. © 2009, 2011, 2013 Freescale Semiconductor, Inc.
Document Number: QP10XXFS REV 6
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
