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8735AYI-01LFT

Description
clock generators & support products 5 lvpecl out divider
Categorysemiconductor    Other integrated circuit (IC)   
File Size272KB,17 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Environmental Compliance  
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8735AYI-01LFT Overview

clock generators & support products 5 lvpecl out divider

Integrated
Circuit
Systems, Inc.
ICS8735I-01
1:5 D
IFFERENTIAL
-
TO
-3.3V LVPECL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
F
EATURES
5 differential 3.3V LVPECL outputs
Selectable differential clock inputs
CLKx, nCLKx pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Output frequency range: 31.25MHz to 700MHz
Input frequency range: 31.25MHz to 700MHz
VCO range: 250MHz to 700MHz
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
External feedback for “zero delay” clock regeneration
with configurable frequencies
Cycle-to-cycle jitter: 40ps (maximum)
Output skew: 55ps (maximum)
Static phase offset: 50ps ± 100ps
3.3V supply voltage
-40°C to 85°C ambient operating temperature
G
ENERAL
D
ESCRIPTION
The ICS8735I-01 is a highly versatile 1:5 Differ-
ential-to-3.3V LVPECL clock generator and a
HiPerClockS™
member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS8735I-01 has a fully integrated PLL and can
be configured as zero delay buffer, multiplier or divider, and
has an output frequency range of 31.25MHz to 700MHz. The
reference divider, feedback divider and output divider are each
programmable, thereby allowing for the following output-to-
input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The
external feedback allows the device to achieve “zero delay”
between the input clock and the output clocks. The PLL_SEL
pin can be used to bypass the PLL for system test and debug
purposes. In bypass mode, the reference clock is routed
around the PLL and into the internal output dividers.
ICS
B
LOCK
D
IAGRAM
PLL_SEL
÷1, ÷2, ÷4, ÷8,
÷16, ÷32, ÷64
P
IN
A
SSIGNMENT
Q0
nQ0
V
CC
PLL_SEL
SEL3
V
CCO
V
CCA
nQ4
V
EE
Q4
0
Q1
nQ1
Q2
nQ2
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
FB_IN
nFB_IN
32 31 30 29 28 27 26 25
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
V
CC
nFB_IN
FB_IN
SEL2
V
EE
nQ0
Q0
V
CCO
0
1
1
Q3
nQ3
24
23
22
V
CCO
Q3
nQ3
Q2
nQ2
Q1
nQ1
V
CCO
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
Q4
nQ4
ICS8735I-01
21
20
19
18
17
SEL0
SEL1
SEL2
SEL3
MR
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
32-Lead VFQFN
5mm x 5mm x 0.95 package body
K Package
Top View
8735AYI-01
www.icst.com/products/hiperclocks.html
1
REV. B NOVEMBER 12, 2004

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