DSPIC33FJ128GP706AI/MR datasheet, PDF

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DSPIC33FJ128GP706AI/MR: Description16-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQCC64, 9 X 9 MM, 0.90 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, PLASTIC, QFN-64; CategoryThe embedded processor and controller Microcontrollers and processors; File Size3MB，362 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com; Environmental Compliance

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DSPIC33FJ128GP706AI/MR Overview

16-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQCC64, 9 X 9 MM, 0.90 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, PLASTIC, QFN-64

DSPIC33FJ128GP706AI/MR Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Microchip
Parts packaging code	QFN
package instruction	HVQCCN, LCC64,.35SQ,20
Contacts	64
Reach Compliance Code	compliant
ECCN code	3A991.A.2
Has ADC	YES
Address bus width
bit size	16
maximum clock frequency	40 MHz
DAC channel	NO
DMA channel	YES
External data bus width
Format	FIXED POINT
JESD-30 code	S-PQCC-N64
JESD-609 code	e3
length	9 mm
Humidity sensitivity level	1
Number of I/O lines	53
Number of terminals	64
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	HVQCCN
Encapsulate equivalent code	LCC64,.35SQ,20
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Certification status	Not Qualified
RAM (number of words)	8192
ROM programmability	FLASH
Maximum seat height	1 mm
speed	40 MHz
Maximum slew rate	90 mA
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	9 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER
Base Number Matches	1

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dsPIC33FJXXXGPX06A/X08A/X10A

16-bit Digital Signal Controllers (up to 256 KB Flash and

30 KB SRAM) with Advanced Analog

Operating Conditions

• 3.0V to 3.6V, -40ºC to +150ºC, DC to 20 MIPS

• 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS

Timers/Output Compare/Input Capture

• Up to nine 16-bit timers/counters. Can pair up to

make four 32-bit timers.

• Eight Output Compare modules configurable as

timers/counters

• Eight Input Capture modules

Core: 16-bit dsPIC33F CPU

•

Code-efficient (C and Assembly) architecture

Two 40-bit wide accumulators

Single-cycle (MAC/MPY) with dual data fetch

Single-cycle mixed-sign MUL plus hardware

divide

Communication Interfaces

• Two UART modules (10 Mbps)

- With support for LIN 2.0 protocols and IrDA

• Two 4-wire SPI modules (15 Mbps)

• Up to two I

C™ modules (up to 1 Mbaud) with

SMBus support

• Up to two Enhanced CAN (ECAN) modules

(1 Mbaud) with 2.0B support

• Data Converter Interface (DCI) module with I

codec support

Clock Management

•

±2% internal oscillator

Programmable PLLs and oscillator clock sources

Fail-Safe Clock Monitor (FSCM)

Independent Watchdog Timer (WDT)

Fast wake-up and start-up

Power Management

• Low-power management modes (Sleep, Idle,

Doze)

• Integrated Power-on Reset and Brown-out Reset

• 2.1 mA/MHz dynamic current (typical)

• 50

μA

current (typical)

Input/Output

• Sink/Source up to 10 mA (pin specific) for stan-

dard V

, up to 16 mA (pin specific) for

non-standard V

OH1

• 5V-tolerant pins

• Selectable open drain, pull-ups, and pull-downs

• Up to 5 mA overvoltage clamp current

• External interrupts on all I/O pins

Advanced Analog Features

• Two ADC modules:

- Configurable as 10-bit, 1.1 Msps with four

S&H or 12-bit, 500 ksps with one S&H

- 18 analog inputs on 64-pin devices and up to

32 analog inputs on 100-pin devices

• Flexible and independent ADC trigger sources

Qualification and Class B Support

• AEC-Q100 REVG (Grade 1 -40ºC to +125ºC)

• AEC-Q100 REVG (Grade 0 -40ºC to +150ºC)

• Class B Safety Library, IEC 60730

Debugger Development Support

•

In-circuit and in-application programming

Two program and two complex data breakpoints

IEEE 1149.2-compatible (JTAG) boundary scan

Trace and run-time watch

Packages

Type

QFN

TQFP

0.50

10x10x1

TQFP

0.50

12x12x1

TQFP

100

0.40

14x14x1

Pin Count

Contact Lead/Pitch

0.50

I/O Pins

Dimensions

9x9x0.9

Note:

All dimensions are in millimeters (mm) unless specified.



2009-2012 Microchip Technology Inc.

DS70593D-page 1

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