DS2502P-E48 datasheet, PDF - EEWORLD Datasheet

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DS2502P-E48: DescriptionOTP ROM, 1KX1, CMOS, PDSO6, TSOC-6; Categorystorage storage; File Size448KB，22 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html

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DS2502P-E48 Overview

OTP ROM, 1KX1, CMOS, PDSO6, TSOC-6

DS2502P-E48 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Maxim
Parts packaging code	SOIC
package instruction	LSOC, SOC6,.17
Contacts	6
Reach Compliance Code	not_compliant
ECCN code	EAR99
I/O type	COMMON
JESD-30 code	R-PDSO-C6
JESD-609 code	e0
length	3.94 mm
memory density	1024 bit
Memory IC Type	OTP ROM
memory width	1
Humidity sensitivity level	1
Number of functions	1
Number of terminals	6
word count	1024 words
character code	1000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	1KX1
Package body material	PLASTIC/EPOXY
encapsulated code	LSOC
Encapsulate equivalent code	SOC6,.17
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, LOW PROFILE
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	240
power supply	3/5 V
Certification status	Not Qualified
Maximum seat height	1.5 mm
Maximum standby current	0.000005 A
Maximum slew rate	0.000005 mA
Maximum supply voltage (Vsup)	6 V
Minimum supply voltage (Vsup)	2.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	C BEND
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	20
width	3.76 mm
Base Number Matches	1

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DS2502

1 kbit Add-Only Memory

www.dalsemi.com

FEATURES

1024 bits Electrically Programmable Read

Only Memory (EPROM) communicates with

the economy of one signal plus ground

Unique, factory-lasered and tested 64-bit

registration number (8-bit family code + 48-

bit serial number + 8-bit CRC tester) assures

absolute traceability because no two parts are

alike

Built-in multidrop controller ensures

compatibility with other MicroLAN products

EPROM partitioned into four 256-bit pages

for randomly accessing packetized data

Each memory page can be permanently

write-protected to prevent tampering

Device is an “add only” memory where

additional data can be programmed into

EPROM without disturbing existing data

Architecture allows software to patch data by

superseding an old page in favor of a newly

programmed page

Reduces control, address, data, power, and

programming signals to a single data pin

Directly connects to a single port pin of a

microprocessor and communicates at up to

16.3 kbits per second

8-bit family code specifies DS2502

communications requirements to reader

Presence detector acknowledges when the

reader first applies voltage

Low cost TO-92 or 8-pin SOIC and TSOC

surface mount package

Reads over a wide voltage range of 2.8V to

6.0V from -40°C to +85°C; programs at

11.5V to 12.0V from -40°C to +50°C

PIN ASSIGNMENT

TO-92

DS2502

DATA

GND

8-PIN SOIC (150 MIL)

TSOC PACKAGE

GND

DATA

GND

DATA

TOP VIEW

3.7 X 4.0 X 1.5 mm

See Mech.

Drawings Section

1 2 3

BOTTOM VIEW

ORDERING INFORMATION

DS2502

DS2502S

DS2502P

DS2502T

DS2502Y

DS2502V

DS2502X1

TO-92 package

8-pin SOIC package

6-pin TSOC package

Tape & Reel version of DS2502

Tape & Reel version of DS2502S

Tape & Reel version of DS2502P

Chip Scale Pkg., Tape & Reel

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102199

DS2502

SILICON LABEL DESCRIPTION

The DS2502 1 kbit Add-Only Memory identifies and stores relevant information about the product to

which it is associated. This lot- or product-specific information can be accessed with minimal interface-

for example, a single port pin of a microcontroller. The DS2502 consists of a factory-lasered registration

number that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit Family Code (09h) plus 1

kbit of EPROM which is user-programmable. The power to program and read the DS2502 is derived

entirely from the 1-Wire

communication line.

Data is transferred serially via the 1-Wire protocol which requires only a single data lead and a ground

return. The entire device can be programmed and then write-protected if desired. Alternatively, the part

may be programmed multiple times with new data being appended to, but not overwriting, existing data

with each subsequent programming of the device. Note: Individual bits can be changed only from a

logical 1 to a logical 0, never from a logical 0 to a logical 1. A provision is also included for indicating

that a certain page or pages of data are no longer valid and have been replaced with new or updated data

that is now residing at an alternate page address. This page address redirection allows software to patch

data and enhance the flexibility of the device as a stand-alone database. The 48-bit serial number that is

factory-lasered into each DS2502 provides a guaranteed unique identity which allows for absolute

traceability. The familiar TO-92 or SOIC or TSOC packages provide a compact enclosure that allows

standard assembly equipment to handle the device easily for attachment to printed circuit boards or

wiring. Typical applications include storage of calibration constants, maintenance records, asset tracking,

product revision status, and access codes.

OVERVIEW

The block diagram in Figure 1 shows the relationships between the major control and memory sections of

the DS2502. The DS2502 has three main data components: 1) 64-bit lasered ROM, 2) 1024-bit EPROM,

and 3) EPROM Status Bytes. The device derives its power for read operations entirely from the 1-Wire

communication line by storing energy on an internal capacitor during periods of time when the signal line

is high and continues to operate off of this “parasite” power source during the low times of the 1-Wire

line until it returns high to replenish the parasite (capacitor) supply. During programming, 1-Wire

communication occurs at normal voltage levels and then is pulsed momentarily to the programming

voltage to cause the selected EPROM bits to be programmed. The 1-Wire line must be able to provide 12

volts and 10 milliamperes to adequately program the EPROM portions of the part. Whenever

programming voltages are present on the 1-Wire line a special high voltage detect circuit within the

DS2502 generates an internal logic signal to indicate this condition. The hierarchical structure of the 1-

Wire protocol is shown in Figure 2. The bus master must first provide one of the six ROM Function

Commands, 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM. These commands operate on

the 64-bit lasered ROM portion of each device and can singulate a specific device if many are present on

the 1-Wire line as well as indicate to the bus master how many and what types of devices are present. The

protocol required for these ROM Function Commands is described in Figure 9. After a ROM Function

Command is successfully executed, the memory functions that operate on the EPROM portions of the

DS2502 become accessible and the bus master may issue any one of the five Memory Function

Commands specific to the DS2502 to read or program the various data fields. The protocol for these

Memory Function Commands is described in Figure 5. All data is read and written least significant bit

first.

64-BIT LASERED ROM

Each DS2502 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code.

The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. (See Figure 3).

The 64-bit ROM and ROM Function Control section allow the DS2502 to operate as a 1-Wire device and

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102199

DS2502

1024-BITS EPROM

The memory map in Figure 5 shows the 1024-bit EPROM section of the DS2502 which is configured as

four pages of 32 bytes each. The 8-bit scratchpad is an additional register that acts as a buffer when

programming the memory. Data is first written to the scratchpad and then verified by reading an 8-bit

CRC from the DS2502 that confirms proper receipt of the data. If the buffer contents are correct, a

programming voltage should be applied and the byte of data will be written into the selected address in

memory. This process ensures data integrity when programming the memory. The details for reading and

programming the 1024-bit EPROM portion of the DS2502 are given in the Memory Function Commands

section.

EPROM STATUS BYTES

In addition to the 1024 bits of data memory the DS2502 provides 64 bits of Status Memory accessible

with separate commands.

The EPROM Status Bytes can be read or programmed to indicate various conditions to the software

interrogating the DS2502. The first byte of the EPROM Status Memory contain the Write Protect Page

bits which inhibit programming of the corresponding page in the 1024-bit main memory area if the

appropriate write protection bit is programmed. Once a bit has been programmed in the Write Protect

Page byte, the entire 32-byte page that corresponds to that bit can no longer be altered but may still be

read.

The next 4 bytes of the EPROM Status Memory contain the Page Address Redirection Bytes, which

indicate if one or more of the pages of data in the 1026-bit EPROM section have been invalidated and

redirected to the page address contained in the appropriate redirection byte. The hardware of the DS2502

makes no decisions based on the contents of the Page Address Redirection Bytes. These additional bytes

of Status EPROM technology, bits within a page can be changed from a logical 1 to a logical 0 by

programming, but cannot be changed back. Therefore, it is not possible to simply rewrite a page if the

data requires changing or updating, but with space permitting, an entire page of data can be redirected to

another page within the DS2502 by writing the one’ complement of the new page address into the Page

Address Redirection Byte that corresponds to the original (replaced) page.

This architecture allows the user’ software to make a “data patch” to the EPROM by indicating that a

particular page or pages should be replaced with those indicated in the Page Address Redirection Bytes.

If a Page Address Redirection Byte has an FFH value, the data in the main memory that corresponds to

that page is valid. If a Page Address Redirection Byte has some other hex value, the data in the page

corresponding to that redirection byte is invalid, and the valid data can now be found at the one’

complement of the page address indicated by the hex value stored in the associated Page Address

Redirection Byte. A value of FDH in the redirection byte for page 1, for example, would indicate that the

updated data is now in page 2. The details for reading and programming the EPROM status memory

portion of the DS2502 are given in the Memory Function Commands section.

MEMORY FUNCTION COMMANDS

The “Memory Function Flow Chart” (Figure 6) describes the protocols necessary for accessing the

various data fields within the DS2502. The Memory Function Control section, 8-bit scratchpad, and the

Program Voltage Detect circuit combine to interpret the commands issued by the bus master and create

the correct control signals within the device. A 3-byte protocol is issued by the bus master. It is

comprised of a command byte to determine the type of operation and two address bytes to determine the

specific starting byte location within a data field. The command byte indicates if the device is to be read

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102199

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