EEWORLDEEWORLDEEWORLD

Part Number

Search

530PB50M0000DGR

Description
CMOS Output Clock Oscillator, 10MHz Min, 945MHz Max, 50MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size127KB,12 Pages
ManufacturerSkyworks
Websitehttp://www.skyworksinc.com
Environmental Compliance
Download Datasheet Parametric View All

530PB50M0000DGR Online Shopping

Suppliers Part Number Price MOQ In stock  
530PB50M0000DGR - - View Buy Now

530PB50M0000DGR Overview

CMOS Output Clock Oscillator, 10MHz Min, 945MHz Max, 50MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530PB50M0000DGR Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Objectid4037668867
package instructionROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Codecompliant
YTEOL6.38
Other featuresTAPE AND REEL
Frequency Adjustment - MechanicalNO
frequency stability20%
JESD-609 codee4
Installation featuresSURFACE MOUNT
Number of terminals6
Maximum operating frequency945 MHz
Minimum operating frequency10 MHz
Nominal operating frequency50 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeCMOS
Package body materialPLASTIC/EPOXY
Encapsulate equivalent codeDILCC6,.2
physical size7.0mm x 5.0mm x 1.85mm
Certification statusNot Qualified
Maximum slew rate88 mA
Maximum supply voltage3.63 V
Minimum supply voltage2.97 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceGold (Au) - with Nickel (Ni) barrier
S i 5 3 0 / 5 31
R
EVISION
D
C
R YS TA L
O
SCILLATOR
(XO) (10 M H
Z
Features
TO
1 . 4 GH
Z
)
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
1
6
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
OE
2
5
CLK–
GND
3
4
CLK+
Si530 (LVDS/LVPECL/CML)
OE
1
6
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
2
5
NC
GND
3
4
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
1
6
V
DD
NC
2
5
CLK–
GND
3
4
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.4 5/13
Copyright © 2013 by Silicon Laboratories
Si530/531
Pengfeng Perf-V Development Board Review Summary
Activity link: Free evaluation of Pengfeng Artix 7 FPGA development kitEvaluation summary ( updated on July 26, 2021 ):@cruelfox[Perf-V Evaluation] Development Board Circuit Analysis and Xilinx Softwa...
okhxyyo FPGA/CPLD
TI official ZStack-2.5.1a based on CC2530
TI official ZStack, based on CC2530...
Gyroxp RF/Wirelessly
I don't know if this problem is negative optimization of AD.
I received a schematic today and was ready to start working on it. But when I opened AD19, it was stuck. The opening speed was OK, but it was stuck when zooming in and out of the schematic. It took a ...
慢摇DJ MCU
EEWORLD University ---- Low Distortion Design (1)
Low Distortion Design (1) : https://training.eeworld.com.cn/course/3710...
hi5 Analog electronics
Boot error after 2440 development board is running stably
The system consists of S3C2440+K9F2G08+64M RAM, and is programmed with ARMVIVI+ LINUX kernel+root file system. (The application is directly on the root file system) After running normally for a period...
tulipyyf ARM Technology
Where is the module power standby loss?
The smaller the ineffective loss, the better. Especially in some instrumentation industries, when selecting module power supplies, the standby power consumption of the module power supply is very high...
fish001 Analogue and Mixed Signal

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 112  1937  781  2650  1600  3  39  16  54  33 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号