531AA267M000DGR datasheet, PDF

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531AA267M000DGR: DescriptionLVPECL Output Clock Oscillator, 10MHz Min, 945MHz Max, 267MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size127KB，12 Pages; ManufacturerSkyworks; Websitehttp://www.skyworksinc.com; Environmental Compliance

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531AA267M000DGR Overview

LVPECL Output Clock Oscillator, 10MHz Min, 945MHz Max, 267MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531AA267M000DGR Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	4037663988
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	compliant
YTEOL	6.5
Other features	TAPE AND REEL
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	50%
JESD-609 code	e4
Installation features	SURFACE MOUNT
Number of terminals	6
Maximum operating frequency	945 MHz
Minimum operating frequency	10 MHz
Nominal operating frequency	267 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	LVPECL
Package body material	PLASTIC/EPOXY
Encapsulate equivalent code	DILCC6,.2
physical size	7.0mm x 5.0mm x 1.85mm
Certification status	Not Qualified
longest rise time	0.35 ns
Maximum slew rate	121 mA
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Gold (Au) - with Nickel (Ni) barrier

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S i 5 3 0 / 5 31

EVISION

R YS TA L

SCILLATOR

(XO) (10 M H

Features



1 . 4 GH

)

Available with any-rate output



frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz



3rd generation DSPLL

with superior



jitter performance



3x better frequency stability than



SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout



Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications



SONET/SDH



Networking



SD/HD video



Test and measurement



Clock and data recovery



FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

GND

CLK+

Si530 (LVDS/LVPECL/CML)

Functional Block Diagram

CLK– CLK+

GND

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

CLK–

GND

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.4 5/13

Si530/531

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