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CH722C475MG80A0

Description
Ceramic Capacitor, Multilayer, Ceramic, 200V, 20% +Tol, 20% -Tol, X7R, 15% TC, 4.7uF, Through Hole Mount, DIP
CategoryPassive components    capacitor   
File Size49KB,1 Pages
ManufacturerAVX
Download Datasheet Parametric View All

CH722C475MG80A0 Overview

Ceramic Capacitor, Multilayer, Ceramic, 200V, 20% +Tol, 20% -Tol, X7R, 15% TC, 4.7uF, Through Hole Mount, DIP

CH722C475MG80A0 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
Objectid1995077235
package instruction,
Reach Compliance Codecompliant
ECCN codeEAR99
capacitance4.7 µF
Capacitor typeCERAMIC CAPACITOR
dielectric materialsCERAMIC
JESD-609 codee0
Installation featuresTHROUGH HOLE MOUNT
multi-layerYes
negative tolerance20%
Number of terminals2
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package shapeRECTANGULAR PACKAGE
positive tolerance20%
Rated (DC) voltage (URdc)200 V
surface mountNO
Temperature characteristic codeX7R
Temperature Coefficient15% ppm/°C
Terminal surfaceTin/Lead (Sn/Pb)
Terminal shapeFLAT
Stacked Leaded MLC Capacitors
CH-CV Series
10nF to 180 µF
BS9100 approved
50V to 500 VDC
Low ESR/ESL
-55ºC to +125ºC
1B/C0G and 2C1/X7R Dielectrics
50-500V ESCC 3001/030
1-3kV ESCC 3001/034
This range allows SMPS engineers to select the best volumetric solution for input and
output filter applications in high reliability designs. Utilizing advanced multilayer ceramic
techniques to minimize ESR/ESL giving high current handling properties appropriate for
filtering, smoothing and decoupling circuits. CH-CV series parts are qualified for ESA.
HOW TO ORDER
CV
Style
Code
52
Size
Code
5
C
106
M
G
3
0
A
2
Voltage Dielectric Capacitance Code Capacitance Specification Code
Finish Code
Lead Dia.
Lead Space Lead Style
Code
Code
(2 significant digits
Tolerance
A = Non-customized 3 = Uncoated
Code
Code
Code
5 = 50V
A = C0G
+ no. of zeros)
J = ±5%
G = 9100
8 = Coated
0 = Standard A = Standard 2 = 2 Terminal
1 = 100V C = X7R Examples:
K = ±10%
(classified as
4 = 4 Terminal
2 = 200V
1 µF = 105
M = ±20%
uninsulated)
This style is
7 = 500V
10 µF = 106
P = -0 +100%
only available
100 µF = 107
in 3 & 4 chip
assemblies
CH
Style
Code
52
Size
Code
5
C
106
M
G
3
0
A
0
Voltage Dielectric Capacitance Code Capacitance Specification Code
Finish Code
Lead Dia.
Lead Space
Lead Style
Code
Code
(2 significant digits
Tolerance
A = Non-customized 3 = Uncoated
Code
Code
Code
5 = 50V
A = C0G
+ no. of zeros)
J = ±5%
G = 9100
8 = Coated
0 = Standard A = Standard 0 = Straight
1 = 100V C = X7R Examples:
K = ±10%
(classified as
dual in line
2 = 200V
1 µF = 105
M = ±20%
uninsulated)
4 = 4 Terminal
7 = 500V
10 µF = 106
P = -0 +100%
100 µF = 107
CAPACITANCE VALUE
CH/CV41-44
50
100
200
500
50
100
200
500
50
100
200
500
50
100
200
500
50
100
200
500
50
100
200
500
50
100
200
500
50
100
200
500
C0G
Min Cap µF
0.068
0.047
0.033
0.01
0.12
0.10
0.068
0.022
0.22
0.15
0.12
0.033
0.39
0.27
0.22
0.068
0.39
0.27
0.22
0.068
0.39
0.27
0.22
0.068
0.68
0.56
0.39
0.12
1.2
1.0
0.82
0.22
C0G
Max Cap µF
0.39
0.33
0.27
0.068
0.68
0.47
0.39
0.1
1.2
1.0
0.68
0.22
2.2
1.8
1.2
0.39
2.2
1.8
1.2
0.39
2.7
2.2
1.8
0.56
3.9
3.3
2.7
0.82
5.6
4.7
3.9
1.5
X7R
Min Cap µF
1.8
1.0
0.33
0.12
3.9
2.2
0.68
0.27
6.8
4.7
1.0
0.47
12
8.2
2.2
0.82
12
8.2
2.2
0.82
15
12
2.2
0.82
22
15
3.9
1.5
39
33
8.2
2.7
X7R
Max Cap µF
12
10
2.2
1.0
22
15
3.9
1.5
39
33
10
3.3
68
47
12
5.6
68
47
12
5.6
82
47
12
5.6
120
68
27
8.2
180
150
39
18
CH/CV51-54
CH/CV61-64
CH/CV71-74
CH/CV76-79
CH/CV81-84
CH/CV86-89
CH/CV91-94
31
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