HCMP96850
SINGLE ULTRAFAST VOLTAGE COMPARATOR
FEATURES
•
•
•
•
Propagation Delay of 2.4 ns (typ)
Propagation Delay Skew <300 ps
Low Offset
±3
mV
Latch Control
APPLICATIONS
•
•
•
•
•
•
High Speed Instrumentation, ATE
High Speed Timing
Window Comparators
Line Receivers
A/D Conversion
Threshold Detection
GENERAL DESCRIPTION
The HCMP96850 is a single, very high speed monolithic
comparator. It is pin-compatible with and has improved
performance over the AD9685 and the AM6685. The
HCMP96850 is designed for use in Automatic Test Equip-
ment (ATE), high speed instrumentation, and other high
speed comparator applications.
Improvements over other sources include reduced power
consumption, reduced propagation delays, and higher input
impedance.
The HCMP96850 is available in a 16-lead ceramic DIP
package over the industrial temperature range. It is also
available in die form.
BLOCK DIAGRAM
LATCH ENABLE
VEE
VCC
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA
Phone: (719) 528-2300 FAX: (719) 528-2370 Website: http://www.spt.com E-Mail: sales@spt.com
-
INVERTING
INPUT
+
NONINVERTING
INPUT
Q OUTPUT
Q OUTPUT
GND1
GND2
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)
1
25
°
C
Supply Voltages
Positive Supply Voltage (V
CC
to GND) .... -0.5 to +6.0 V
Negative Supply Voltage (V
EE
to GND) ... -6.0 to +0.5 V
Ground Voltage Differential ...................... -0.5 to +0.5 V
Input Voltages
Input Voltage ............................................ -4.0 to +4.0 V
Differential Input Voltage .......................... -5.0 to +5.0 V
Input Voltage, Latch Controls ..................... V
EE
to 0.5 V
Output
Output Current ...................................................... 30 mA
Temperature
Operating Temperature, ambient ............. -25 to +85
°C
junction ...................... +150
°C
Lead Temperature, (soldering 60 seconds) ...... +300
°C
Storage Temperature .............................. -65 to +150
°C
Note:
1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal
applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
T
A
= +25
°C,
V
CC
= +5.0 V, V
EE
= -5.2 V, R
L
= 50 Ohms, unless otherwise specified.
PARAMETERS
TEST
CONDITIONS
TEST
LEVEL
MIN
TYP
MAX
UNITS
DC ELECTRICAL CHARACTERISTICS
Input Offset Voltage
Input Offset Voltage (V
os
)
(V
os
) Tempco
Input Bias Current
Input Bias Current
Input Offset Current
Input Offset Current
Positive Supply Current
Negative Supply Current
Positive Supply Voltage, V
CC
Negative Supply Voltage, V
EE
Input Common Mode Range
Latch Enable
Common Mode Range
Open Loop Gain
Input Resistance
Input Capacitance
Input Capacitance
Power Supply Sensitivity
Common Mode Rejection Ratio
Power Dissipation
I
OUTPUT
= 0 mA
(LCC Package)
V
CC
and V
EE
IV
V
V
V
V
V
V
IV
-2
4000
60
3
1
70
80
90
120
0
V
V/V
kΩ
pF
pF
dB
dB
mW
T
MIN
<T
A
<T
MAX
T
MIN
<T
A
<T
MAX
R
S
= 0 Ohms
1
R
S
= 0 Ohms,
1
T
MIN
<T
A
<T
MAX
IV
V
I
IV
I
IV
I
I
IV
IV
I
+4.75
-4.95
-2.5
-1.0
-1.5
3.3
13.5
+5.0
-5.2
-3.5
4
4
7
+1.0
+1.5
5
18
+5.25
-5.45
+2.5
±20
+3.5
mV
µV/°C
µA
µA
µA
µA
mA
mA
V
V
V
IV
-3
+3
mV
SPT
HCMP96850
2
3/18/97
ELECTRICAL SPECIFICATIONS
T
A
= +25
°C,
V
CC
= +5.0 V, V
EE
= -5.2 V, R
L
= 50 Ohms, unless otherwise specified.
PARAMETERS
TEST
CONDITIONS
TEST
LEVEL
MIN
TYP
MAX
UNITS
OUTPUT LOGIC LEVELS (ECL 10 KH Compatible)
Output High
Output Low
50 Ohms to -2 V
50 Ohms to -2 V
I
I
-.98
-1.95
-.81
-1.63
V
V
AC ELECTRICAL CHARACTERISTICS
2
Propagation Delay
Latch Set-up Time
Latch to Output Delay
Latch Pulse Width
Latch Hold Time
Rise Time
Fall Time
1
R
S
= source impedance.
2
100 mV input step.
10 mV O.D.
III
IV
2.4
0.6
3.0
1
3
ns
ns
ns
ns
50 mV O.D.
IV
V
IV
2
0.5
1.76
1.76
ns
ns
ns
20% to 80%
20% to 80%
V
V
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
TEST LEVEL
I
II
III
IV
V
VI
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at T
A
=25
°C,
and sample
tested at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design
and characterization data.
Parameter is a typical value for information purposes
only.
100% production tested at T
A
= 25
°C.
Parameter is
guaranteed over specified temperature range.
SPT
HCMP96850
3
3/18/97
TIMING INFORMATION
The timing diagram for the comparator is shown in figure 1.
The latch enable (LE) pulse is shown at the top. If LE is high
in the HCMP96850, the comparator tracks the input differ-
ence voltage. When LE is driven low, the comparator out-
puts are latched into their existing logic states.
The leading edge of the input signal (which consists of a
10 mV overdrive voltage) changes the comparator output
after a time of t
pdL
or t
pdH
(Q or
Q
). The input signal must be
maintained for a time t
s
(set-up time) before the latch enable
falling edge and held for time t
H
after the falling edge for the
comparator to accept data. After t
H
, the output ignores the
input status until the latch is strobed again. A minimum latch
pulse width of t
pL
is needed for strobe operation, and the
output transitions occur after a time of t
pLOH
or t
pLOL
.
Figure 1 - Timing Diagram
50%
LATCH ENABLE
t
H
t
S
DIFFERENTIAL
INPUT VOLTAGE
V
OD
t
pdL
OUTPUT Q
t
pLOH
50%
VREF ± VOS
t
pL
OUTPUT Q
t
pdH
V
IN
+=100 mV (P-P), V
OD
=10 mV
t
pLOL
50%
The set-up and hold times are a measure of the time required for an input signal to propagate through the first
stage of the comparator to reach the latching circuitry. Input signal changes occurring before t
S
will be detected
and held; those occurring after t
H
will not be detected. Changes between t
S
and t
H
may or may not be detected.
SWITCHING TERMS (Refer to figure 1)
t
pdH
INPUT TO OUTPUT HIGH DELAY - The propagation
delay measured from the time the input signal crosses
the input reference voltage (± the input offset voltage)
to the 50% point of an output LOW to HIGH transition.
INPUT TO OUTPUT LOW DELAY - The propagation
delay measured from the time the input signal crosses
the input reference voltage (± the input offset voltage)
to the 50% point of an output HIGH to LOW transition.
LATCH ENABLE TO OUTPUT HIGH DELAY - The
propagation delay measured from the 50% point of the
Latch Enable signal LOW to HIGH transition to 50%
point of an output LOW to HIGH transition.
VOLTAGE OVERDRIVE - The difference between the
differential input and reference input voltages.
t
pLOL
LATCH ENABLE TO OUTPUT LOW DELAY - The
propagation delay measured from the 50% point of the
Latch Enable signal LOW to HIGH transition to the 50%
point of an output HIGH to LOW transition.
MINIMUM HOLD TIME - The minimum time after the
negative transition of the Latch Enable signal that the
input signal must remain unchanged in order to be
acquired and held at the outputs.
MINIMUM LATCH ENABLE PULSE WIDTH - The
minimum time that the Latch Enable signal must be
HIGH in order to acquire an input signal change.
MINIMUM SET-UP TIME - The minimum time before
the negative transition of the Latch Enable signal that
an input signal change must be present in order to be
acquired and held at the outputs.
t
pdL
t
H
t
pLOH
t
pL
t
S
V
OD
SPT
HCMP96850
4
3/18/97
Figure 2 - Internal Function Diagram
TYPICAL INTERFACE CIRCUIT
A typical interface circuit using the comparator is shown in
figure 3. Although it needs few external components and is
easy to apply, there are several considerations that should
be noted to achieve optimal performance. The very high
operating speeds of the comparator require careful layout,
decoupling of supplies, and proper design of transmission
lines.
Since the HCMP96850 comparator is a very high frequency
and high gain device, certain layout rules must be followed
to avoid spurious oscillations. The comparator should be
soldered to the board with component lead lengths kept as
short as possible. A ground plane should be used, while the
input impedance to the part is kept as low as possible, to
decrease parasitic feedback. If the output board traces are
longer than approximately one-half inch, microstripline tech-
niques must be employed to prevent ringing on the output
waveform. Also, the microstriplines must be terminated at
the far end with the characteristic impedance of the line to
prevent reflections. All voltage supply pins should be de-
coupled with high-frequency capacitors as close to the
device as possible. All ground pins and no connects should
be connected to a common ground plane to further improve
noise immunity.
On the HCMP96850, all outputs, whether used or unused,
should have identical terminations to minimize ground cur-
rent switching.
Q
V
IN
+
-
PRE
AMP
LATCH
ECL
OUT
V
IN
REF1
REF
2
CLK
BUF
V
EE
V
CC
GND
1
LE
GND
2
GENERAL INFORMATION
The HCMP96850 is an ultrahigh speed single voltage com-
parator. It offers tight absolute characteristics which guaran-
tee matching from package to package. The device has
differential analog inputs and complementary logic outputs
compatible with ECL systems. The output stage is adequate
for driving terminated 50 Ohm transmission lines.
The HCMP96850 has one latch enable control and should be
driven by standard ECL logic levels. It also has two separate
ground pins, one for the output to accommodate large
ground currents without affecting the rest of the circuit, while
the other is for the small signal intermediate stages. The
input stage is referenced to V
CC
and V
EE
.
Figure 3 - Typical Interface Circuit
VCC GND1 VEE
.1 µF
Noninverting
Input
VIN
VREF
Inverting
Input
+
-
GND2
LE
-2 V
Pulldown
RL
Q Output
Q Output
50
Ω
50
Ω
.1
µF
= Represents line termination.
SPT
HCMP96850
5
3/18/97
京公网安备 11010802033920号
EEWORLD
