R1QEA7218ABG-22IT datasheet, PDF

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R1QEA7218ABG-22IT: DescriptionDDR SRAM; Categorystorage storage; File Size885KB，39 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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R1QEA7218ABG-22IT Overview

DDR SRAM

R1QEA7218ABG-22IT Parametric

Parameter Name	Attribute value
Objectid	1292990655
package instruction	LBGA,
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	0.45 ns
JESD-30 code	R-PBGA-B165
length	17 mm
memory density	75497472 bit
Memory IC Type	DDR SRAM
memory width	18
Number of functions	1
Number of terminals	165
word count	4194304 words
character code	4000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	4MX18
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Maximum seat height	1.4 mm
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	15 mm

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R1QBA72 / R1QEA72 Series

R1QBA7236ABG / R1QBA7218ABG

R1QEA7236ABG / R1QEA7218ABG

72-Mbit DDRII+ SRAM

2-word Burst

Description

The R1Q#A7236 is a 2,097,152-word by 36-bit and the R1Q#A7218 is a 4,194,304-word by 18-bit synchronous

double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor

memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are

controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products

are suitable for applications which require synchronous operation, high speed, low voltage, high density and

wide bit configuration. These products are packaged in 165-pin plastic FBGA package.

= B: Latency =2.5, w/o ODT

= E: Latency =2.5, w/ ODT

# = H: Latency =2.0, w/o ODT

# = L: Latency =2.0, w/ ODT

R10DS0181EJ0011

Rev. 0.11

2013.01.15

Features

Power Supply

• 1.8 V for core (V

), 1.4 V to V

for I/O (V

DDQ

)

Clock

• Fast clock cycle time for high bandwidth

• Two input clocks (K and /K) for precise DDR timing at clock rising edges only

• Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems

• Clock-stop capability with

μs

restart

I/O

• Common data input/output bus

• Pipelined double data rate operation

• HSTL I/O

• User programmable output impedance

• DLL/PLL circuitry for wide output data valid window and future frequency scaling

• Data valid pin (QVLD) to indicate valid data on the output

Function

• Two-tick burst for low DDR transaction size

• Internally self-timed write control

• Simple control logic for easy depth expansion

• JTAG 1149.1 compatible test access port

Package

• 165 FBGA package (15 x 17 x 1.4 mm)

Notes:

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress

Semiconductor, IDT, Samsung, and Renesas Electronics Corp. (QDR Co-Development Team)

2. The specifications of this device are subject to change without notice. Please contact your nearest

Renesas Electronics Sales Office regarding specifications.

3. Refer to

"http://www.renesas.com/products/memory/fast_sram/qdr_sram/index.jsp"

for the latest and detailed information.

4. Descriptions about x9 parts in this datasheet are just for reference.

Rev. 0.11 : 2013.01.15

R10DS0181EJ0011

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