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P4C1049L-70L36M

Description
Standard SRAM, 512KX8, 70ns, CMOS, CDSO36, 0.452 X 0.920 INCH, CERAMIC, LCC-36
Categorystorage    storage   
File Size878KB,12 Pages
ManufacturerPyramid Semiconductor Corporation
Websitehttp://www.pyramidsemiconductor.com/
Download Datasheet Parametric View All

P4C1049L-70L36M Overview

Standard SRAM, 512KX8, 70ns, CMOS, CDSO36, 0.452 X 0.920 INCH, CERAMIC, LCC-36

P4C1049L-70L36M Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerPyramid Semiconductor Corporation
Parts packaging codeDLCC
package instructionSON,
Contacts36
Reach Compliance Codecompliant
ECCN code3A001.A.2.C
Maximum access time70 ns
JESD-30 codeR-CDSO-N36
JESD-609 codee0
length23.368 mm
memory density4194304 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals36
word count524288 words
character code512000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize512KX8
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeSON
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height2.54 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formNO LEAD
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width11.4935 mm
Base Number Matches1
P4C1049/P4C1049L
HIGH SPEED 512K x 8
STATIC CMOS RAM
FEaturES
High Speed (Equal access and cycle times)
— 15/20/25 ns (commercial)
— 20/25/35 ns (industrial)
— 20/25/35/45/55/70 ns (military)
low Power
Single 5V±10% Power Supply
Easy memory Expansion using
CE
and
OE
inputs
common Data i/o
three-State outputs
Fully ttl compatible inputs and outputs
advanced cmoS technology
automatic Power Down
Packages
—36-Pin ceramic DiP (600 mil)
—36-Pin SoJ (400 mil)
—36-Pin FlatPack
—36-Pin lcc (452 mil x 920 mil)
DEScriPtion
The P4C1049 is a 4 Megabit high-speed CMOS static RAM
organized as 512Kx8. The CMOS memory requires no
clocks or refreshing, and has equal access and cycle times.
Inputs are fully TTL-compatible. The RAM operates from
a single 5V±10% tolerance power supply.
Access times as fast as 15 nanoseconds permit greatly
enhanced system operating speeds. CMOS is utilized to
reduce power consumption to a low level. The P4C1049
is a member of a family of PACE RAM™ products offering
fast access times.
The P4C1049 device provides asynchronous operation
with matching access and cycle times. Memory locations
are specified on address pins A
0
to A
18
. Reading is accom-
plished by device selection (CE) and output enabling (OE)
while write enable (WE) remains HIGH. By presenting the
address under these conditions, the data in the addressed
memory location is presented on the data input/output pins.
The input/output pins stay in the HIGH Z state when either
CE
or
OE
is HIGH or
WE
is LOW.
Functional Block Diagram
Pin conFigurationS
SOLDER-SEAL FLAT-
PACK (FS-4),
SOJ (J9, CJ2)
LCC (L11)
DIP PIn-OuT InSIDE DATASHEET
Document #
SRAM128
REV C
Revised August 2011
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