EEWORLDEEWORLDEEWORLD

Part Number

Search

PT7V4050TATFA19.440/19.440

Description
PLL/Frequency Synthesis Circuit,
CategoryAnalog mixed-signal IC    The signal circuit   
File Size156KB,7 Pages
ManufacturerDiodes Incorporated
Download Datasheet Parametric View All

PT7V4050TATFA19.440/19.440 Overview

PLL/Frequency Synthesis Circuit,

PT7V4050TATFA19.440/19.440 Parametric

Parameter NameAttribute value
MakerDiodes Incorporated
package instructionDIP,
Reach Compliance Codecompliant
Other featuresSEATED HEIGHT CALCULATED
Analog Integrated Circuits - Other TypesPHASE DETECTOR
JESD-30 codeR-PDIP-T16
length20.32 mm
Number of functions1
Number of terminals16
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
Maximum seat height4.58 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
Temperature levelINDUSTRIAL
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
width7.62 mm
Base Number Matches1
Data Sheet
PT7V4050
PLL with quartz stabilized VCXO
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Features
PLL with quartz stabilized VCXO
Loss of signals alarm
Return to nominal clock upon LOS
Input data rates from 8 kb/s to 65 Mb/s
Tri-state output
User defined PLL loop response
NRZ data compatible
Single +5.0V power supply
Description
The device is composed of a phase-lock loop with an
integrated VCXO for use in clock recovery, data re-
timing, frequency translation and clock smoothing
applications in telecom and datacom systems.
Crystal Frequencies Supported: 12.000~50.000 MHz.
Block Diagram
CLKIN
DATAIN
HIZ
Phase Detector &
Loss Of Signal
Circuit
RCLK
RDATA
LOS
PHO
VC
LOSIN
CLK1
VCXO
Divider
CLK2
OPN
Op
Amp
OPOUT
OPP
Ordering Information
PT7V4050
Device Type
16-pin clock recoverymodule
PackageLeads
T: Thru-Hole
G: Surface Mount
CLK2 Divider
A: Divide by 2 E: Divide by 32
B: Divide by 4 F: Divide by 64
C: Divide by 8 G: Divide by 128
D: Divide by 16 H: Divide by 256
K: Disable
T
B
C
G
A
49.408 / 12.352
CLK2 Frequency
CLK1 Frequency
A: 5.0V supply voltage
B: 3.3V supply voltage
C:
±
20ppm
F:
±
32ppm
G:
±
50ppm
H:
±
100ppm
Temperature Range
C: 0
°
C to 70
°
C
T: -40
°
C to 85
°
C
12.000
16.128
18.432
22.579
28.000
34.368
44.736
Frequencies using at CLK1 (MHz)
12.288
12.624
13.00
16.384
16.777
16.896
18.936
20.000
20.480
24.576
24.704
25.000
30.720
32.000
32.768
38.880
40.000
41.2416
47.457
49.152
49.408
19.440
35.328
16.000
17.920
22.1184
27.000
33.330
41.943
50.000
40.960
Note:
CLK1 up to 40.960MHz for both 5V and
3.3V for temperature -40oC to 85 oC; CLK1 up to
50MHz for both 5V and 3.3V for temperature 0oC to 70oC.
PT0125(02/06)
1
Ver:2
Graduation Project of Flammable Gas Voice Alarm Based on AT89C51
Help_Graduation project of flammable gas alarm based on at89c51...
465862375 51mcu
[FM33LG0 Series Development Board Review] 05.I2C, SPI
1. Introduction The FM33LG0 series MCU has at most 1 I2C interface supporting master-slave mode and 3 SPI interfaces supporting master-slave mode; I2C supports 7-bit or 10-bit slave addresses, and sup...
xld0932 Domestic Chip Exchange
Has anyone used SM32 to make a smartcard? I used st8024
I followed the official procedure and used UART2 instead. I can detect the card, but I can't receive the ATR information. Does anyone have experience in this area? Please give me some advice! Urgent h...
hlm0610 stm32/stm8
Analysis of major events in the semiconductor industry in the first quarter of 2010 (Part 2)
Toshiba and Nantong Fujitsu jointly set up "Wuxi Tongzhi Company"Toshiba Semiconductor (Wuxi), a subsidiary of Toshiba, and Nantong Fujitsu have reached an agreement to set up the joint venture "Wuxi ...
天天谈芯 Talking
Keep going in 2018! 666~~~
...
chenzhufly Talking
GD32L233C-START Review——08.Desktop Clock——Comprehensive Demo1
[i=s] This post was last edited by wadeRen on 2022-4-3 20:21 [/i] [TOC] # [Article Navigation] [GD32L233C-START Evaluation——01. Unboxing, Development Kit](https://bbs.eeworld.com.cn/thread-1192154-1-1...
wadeRen GD32 MCU

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 600  2605  2127  1766  2054  13  53  43  36  42 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号