Vectron’s VC-709 Crystal Oscillator is a quartz stabilized, differential output oscillator, operating off a 2.5 or 3.3 volt supply in a
hermetically sealed 7x5 ceramic package.
Features
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Ultra Low Jitter Performance, 3rd OT or Fundamental Crystal Design
13.500-220.0000MHz Output Frequencies
Low Power
400ps max Rise and Fall Time
Excellent Power Supply Rejection Ratio
Enable/Disable
3.3 or 2.5V operation
-10/70°C or -40/85°C Operation
Hermetically Sealed 7.0x5.0 mm Ceramic Package
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Applications
PCI Express
Ethernet, GbE, Synchronous Ethernet
Fiber Channel
Enterprise Servers
Telecom
Clock source for A/D’s, D/A’s
Driving FPGA’s
Test and Measurement
PON
Medical
COTS
• Product is compliant to RoHS directive
and fully compatible with lead free assembly
Block Diagram
Complementary
Output
Output
V
DD
Voltage Regulator
Crystal
Phase Noise
Oscillator
E/D or NC E/D or NC
GND
Page1
Performance Specifications
Table 1. Electrical Performance, LVPECL Option
Parameter
Voltage
1
Current
2
, 3.3V
2.5V
Nominal Frequency : 3.3V Supply
2.5V Supply
Stability
3
(Ordering Option)
Outputs
Output Logic Levels
2
Output Logic High
Output Logic Low
Output Rise and Fall Time
2
Load
Duty Cycle
4
Jitter
5
, 156.250MHz
12kHz-50MHz
12kHz -20MHz
10kHz-1MHz
Period Jitter
6
, 156.250MHz,
RMS
P/P
Cycle-Cycle
6
RMS
P/P
Random Jitter
7
Deterministic Jitter
7
Outputs Enabled
8
Outputs Disabled
Disable Time
Enable/Disable Leakage Current
Start-Up Time
Operating Temp. (Ordering Option)
Package Size
t
SU
T
OP
-10/70 or -40/85
7.0 x 5.0 x 1.5
фJ
200
150
100
фJ
1.1
10.5
1.9
17.7
2.2
0
Enable/Disable
V
IH
V
IL
t
D
0.7*V
DD
0.3*V
DD
200
±200
10
V
V
ns
uA
ms
°C
mm
2.2
21.0
3.8
35.4
4.4
ps
ps
ps
ps
ps
ps
fs
fs
fs
45
V
OH
V
OL
t
R
/t
F
50 ohms into V
DD
-2.0V
55
%
V
DD
-1.025
V
DD
-1.810
V
DD
-0.880
V
DD
-1.650
400
V
V
ps
Symbol
V
DD
I
DD
Min
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
45
42
Units
V
V
mA
Frequency
f
N
13.5
125.0
±20, ±25, ±50 or ±100
220.000
220.000
MHz
ppm
1. The VC-709 power supply pin should be filtered, eg, a 10uf, 0.1uf and 0.01uf capacitor.
2. Figure 1 defines the test circuit and Figure 2 defines these parameters.
3. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR reflow.
4. Duty Cycle is defined as the On/Time Period.
5. Measured using an Agilent E5052.
6. Measured using a LeCroy Wavemaster 8600A, 90K samples
7. Measured using a Wavecrest SIA3300C, 90K samples.
8. Outputs will be Enabled if Enable/Disable is left open.
V
DD
-1.3V
t
R
t
F
1
NC
2
NC
3
6
5
4
50
50
V
AMP
*0.8
Cross Point
V
AMP
*0.2
On Time
Period
V
AMP
-1.3V
Figure 1.
Page2
Figure 2.
Performance Specifications
Table 2. Electrical Performance, LVDS Option
Parameter
Voltage
1
Current
2
, 3.3V
2.5V
Nominal Frequency
Stability
3
(Ordering Option)
Outputs
Output Logic Levels
2
Output Logic High
Output Logic Low
Output Amplitude
Differential Output Error
Offset Voltage
Offset Voltage Error
Output Leakage Current, Outputs Disabled
Output Rise and Fall Time
3
Load
Duty Cycle
4
Jitter
5
, 156.250MHz
12kHz - 50MHz
12kHz - 20MHz
10kHz - 1MHz
Period Jitter
6
, 156.250MHz
RMS
P/P
Cycle-Cycle Jitter
6
RMS
P/P
Random Jitter
7
Deterministic Jitter
7
Outputs Enabled
8
Outputs Disabled
Disable Time
Enable/Disable Leakage Current
Start-Up Time
Operating Temp. (Ordering Option)
Package Size
фJ
200
150
100
фJ
1.1
10.5
1.9
17.7
2.2
0
Enable/Disable
V
IH
V
IL
t
D
I
E/D
t
SU
T
OP
-10/70 or -40/85
7.0 x 5.0 x 1.5
0.7*V
DD
0.3*V
DD
200
±200
10
V
V
ns
uA
ms
°C
mm
2.2
21.0
3.8
35.4
4.4
ps
ps
ps
ps
ps
ps
fs
fs
fs
45
t
R
/t
F
100 ohms differential
55
%
1.125
1.25
V
OH
V
OL
1.43
1.10
350
1.6
450
50
1.375
50
10
400
V
V
mV
mV
V
mV
uA
ps
Symbol
Supply
V
DD
I
DD
Min
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
17
14
Units
V
V
mA
Frequency
f
N
13.5
±20, ±25, ±50 or ±100
220.000
MHz
ppm
0.9
250
1.
The VC-709 power supply pin should be filtered, eg, a 10uf, 0.1uf and 0.01uf capacitor.
2. Figure 2 defines these parameters and Figure 3 defines the test circuit.
3. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR reflow.
4. Duty Cycle is defined as the On/Time Period.
5. Measured using an Agilent E5052.
6. Measured using a LeCroy Wavemaster 8600A, 90K samples.
7. Measured using a Wavecrest SIA3300C, 90K samples.
8. Outputs will be Enabled if Enable/Disable is left open.
6
0.01 uF
1
DC
Out
50
50
Out
5
2
4
3
Figure 3.
Page3
Performance Specifications
Table 3. Electrical Performance, HCSL Output
Parameter
Voltage
1
Current
2
Nominal Frequency
Stability
3
(Ordering Options)
Outputs
Output High, 3.3V
Output High, 2.5V
Output Low
Output Logic Swing, 3.3V
Output Logic Swing, 2.5V
Output Rise and Fall Time
3
Load
Duty Cycle
4
Jitter
5
(12 kHz - 20 MHz ) 100.000MHz
Jitter
6
, 100.000MHz
Outputs Enabled
8
Outputs Disabled
Disable Time
Enable/Disable Leakage Current
Start-Up Time
Operating Temp. (Ordering Option)
Package Size
фJ
фJ
V
IH
V
IL
t
D
I
E/D
t
SU
T
OP
-10/70 or -40/85
7.0 x 5.0 x 1.5
PCIe Gen1-Gen5 Compliant
Enable/Disable
0.7*V
DD
0.3*V
DD
200
±200
10
V
V
ns
uA
ms
°C
mm
45
V
OH
V
OL
V
OPP
t
R
/t
F
50 ohms to ground
55
300
%
fs
600
580
-150
0.65
0.60
500
850
850
150
mV
mV
mV
V
V
ps
Symbol
V
DD
I
DD
Min
Supply
2.375
3.165
Frequency
Typical
2.5
3.3
Maximum
2.625
3.465
39
Units
V
V
mA
MHz
ppm
f
N
13.5
±25, ±50 or ±100
170
1. The VC-709 power supply pin should be filtered, e.g., a 10uf, 0.1uf and 0.01uf capacitor.
2. Figure 4 defines the test circuit and Figure 5 defines these parameters.
3. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR reflow.
4. Duty Cycle is defined as the On Time/Period.
5. Measured using an Agilent E5052.
6. Measured using a LeCroy Wavemaster 8600A, 90K samples.
7. Measured using a Wavecrest SIA3300C, 90K samples.
8. Outputs will be Enabled if the Enable/Disable pad is left open.
t
R
1
2
3
6
5
4
50 Ω
50 Ω
t
F
0.8*Vopp
Cross Point
0.2*Vopp
On Time
Period
V
AMP
Figure 4.
Page4
Figure 5.
Package and Pinout
Table 4. Pinout
Pin #
1
2
3
4
5
6
Symbol
E/D or NC
E/D or NC
GND
f
O
Cf
O
V
DD
Function
Enable/Disable or No Connection
Enable/Disable or No Connection
Electrical and Lid Ground
Output Frequency
Complementary Output Frequency
Supply Voltage
Marking Information
XXXMXX - Frequency (Example: 100M00)
YY - Year of Manufacture
WW - Week of the Year
C - Manufacturing Location
Δ - Pin 1 Indicator
7.0±0.15
5
6
4
Table 5. Enable Disable Function
E/D Pin
High
Open
Low
Output
Clock Output
Clock Output
High Impedance
1.96
1
VC-709
XXMXXX
YYWW C
5.0±0.15
2
1.40
3
1.10
1.7 max
1
3.66
6
1.78
Dimensions are in mm
2.54
5.08
Figure 6. Pad Layout
2
3
Bottom View
5
4
3.7
2.54
5.08
Figure 7. Package Outline Drawing
HCSL Application Diagrams
15mA
1
2
3
6
5
4
50 Ω
Z
L
=50 ohms
Z
L
=50 ohms
50 Ω
1
2
3
6
10-30 Ω
5
10-30 Ω
4
50 Ω
Z
L
=50 ohms
50 Ω
Z
L
=50 ohms
Figure 8.
Standard HCSL Output Configuration
Figure 9.
Single Resistor Termination Scheme
Figure 10.
In some cases a 10-30 ohm series resistor is
used to help reduce overshoot.
The VC-709 incorporates a standard High Speed Current Logic, HCSL ,output scheme which is a 15mA current source switched between Out and Comple-
mentary Out. Being un-terminated drains, as shown in Figure 8, they require external 50 ohm resistors to ground as shown in Figure 9. HCSL is a high im-
pedance output with quick switching times, in can be advantageous to use a 10 to 30 ohm series resistor as shown in Figure 10, to help reduce overshoot/
ringing.
One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-termi-
nated, and if it one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching
into account. Load matching and power supply noise are the main contributors to jitter related problems.
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