S i5 2111- B5/ B 6
PCI-E
XPRESS
G
EN
3 S
INGLE
O
UTPUT
C
LOCK
G
ENERATOR
Features
PCI-Express Gen 1, Gen 2,
Gen 3, and Gen 4 common clock
compliant
Gen 3 SRNS Compliant
Low power HCSL differential
output buffer
Supports Serial-ATA (SATA) at
100 MHz
No termination resistors required
25 MHz Crystal Input or Clock
input
Triangular spread spectrum
profile for maximum EMI
reduction (Si52111-B6)
Extended Temperature:
–40 to 85 °C
3.3 V Power supply
Small package 10-pin TDFN
(3x3 mm)
Si52111-B5 does not support
spread spectrum outputs
Si52111-B6 supports 0.5% down
spread outputs
Ordering Information:
See page 13
Applications
Network Attached Storage
Multi-function Printer
Wireless Access Point
Routers
Pin Assignments
Description
Si52111-B5/B6 is a high-performance, PCIe clock generator that can
source one PCIe clock output from a 25 MHz crystal or clock input. The
clock output is compliant to PCIe Gen 1, Gen 2, Gen 3, Gen 3 SRNS and
Gen 4 common clock specifications. The ultra-small footprint (3x3 mm)
and industry leading low power consumption make Si52111-B5/B6 the
ideal clock solution for consumer and embedded applications. Measuring
PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter
Tool. Download it for free at
www.silabs.com/pcie-learningcenter.
VDD
XOUT
XIN/CLKIN
VSS
VSS
1
2
3
4
5
10
9
8
7
6
VDD
NC
NC
DIFF1
DIFF1
Functional Block Diagram
Patents pending
VDD
XIN/CLKIN
XOUT
PLL
Divider
DIFF1
VSS
Rev 1.2 12/15
Copyright © 2015 by Silicon Laboratories
Si52111-B5/B6
Si52111-B5/B6
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. Crystal Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1. Crystal Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2. Calculating Load Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1. 10-Pin TDFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2. 8-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1. TDFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.2. TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7. Recommended Design Guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Rev 1.2
3
Si52111 -B5/B6
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Supply Voltage (extended)
Supply Voltage (commercial)
Symbol
V
DD(extended)
V
DD(commercial)
Test Condition
3.3 V ± 5%
3.3 V ± 10%
Min
3.13
2.97
Typ
3.3
3.3
Max
3.46
3.63
Unit
V
V
Table 2. DC Electrical Specifications
Parameter
Operating Voltage
Operating Supply Current
Input Pin Capacitance
Output Pin Capacitance
Symbol
V
DD
I
DD
C
IN
C
OUT
Test Condition
3.3 V ± 10%
Full Active
Input Pin Capacitance
Output Pin Capacitance
Min
2.97
—
—
—
Typ
3.30
—
3
—
Max
3.63
13
5
5
Unit
V
mA
pF
pF
Table 3. AC Electrical Specifications
Parameter
Crystal
Long-term Accuracy
Clock Input
CLKIN Duty Cycle
CLKIN Rise and Fall Times
CLKIN Cycle-to-Cycle Jitter
CLKIN Long Term Jitter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
DIFF Clocks
Duty Cycle
Symbol
L
ACC
T
DC
T
R
/T
F
T
CCJ
T
LTJ
V
IH
V
IL
I
IH
I
IL
T
DC
T
SKEW
F
OUT
F
ACC
t
r/f2
Test Condition
Measured at V
DD
/2 differential
Measured at V
DD
/2
Measured between 0.2 V
DD
and
0.8 V
DD
Measured at V
DD
/2
Measured at V
DD
/2
XIN/CLKIN pin
XIN/CLKIN pin
XIN/CLKIN pin, VIN = V
DD
XIN/CLKIN pin, 0 < VIN <0.8
Measured at 0 V differential
Measured at 0 V differential
VDD = 3.3 V
All output clocks
Min
—
45
0.5
—
—
2
—
—
–35
45
—
—
—
0.6
Typ
—
—
—
—
—
—
—
—
—
—
—
100
Max
250
55
4.0
250
350
V
DD
+0.3
0.8
35
—
55
60
—
100
4.0
Unit
ppm
%
V/ns
ps
ps
V
V
uA
uA
%
ps
MHz
ppm
Skew
Output Frequency
Frequency Accuracy
Slew Rate
—
—
Measured differentially from
±150 mV
V/ns
Notes:
1.
Visit
www.pcisig.com
for complete PCIe specifications.
2.
Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5
3.
Download the Silicon Labs PCIe Clock Jitter Tool at
www.silabs.com/pcie-learningcenter.
4
Rev 1.2
Si52111-B5/B6
Table 3. AC Electrical Specifications (Continued)
Parameter
Cycle-to-Cycle Jitter
PCIe Gen 1 Pk-Pk Jitter,
Common Clock
PCIe Gen 2 Phase Jitter,
Common Clock
PCIe Gen 3 Phase Jitter,
Common Clock
PCIe Gen 3 Phase Jitter,
Separate Reference No Spread,
SRNS
PCIe Gen 4 Phase Jitter,
Common Clock
Crossing Point Voltage at 0.7 V
Swing
Voltage High
Voltage Low
Spread Range
Modulation Frequency
Enable/Disable and Set-up
Clock Stabilization from
Power-up
Stopclock Set-up Time
T
STABLE
T
SS
—
10.0
—
—
3
—
ms
ns
Symbol
T
CCJ
Pk-Pk
GEN1
Test Condition
Measured at 0 V differential
PCIe Gen 1
10 kHz < F < 1.5 MHz
1.5 MHz < F < Nyquist
Includes PLL BW 2–4 MHz,
CDR = 10 MHz
PLL BW of 2–4 or 2–5 MHz,
CDR = 10 MHz
PLL BW of 2–4 or 2–5 MHz,
CDR = 10 MHz
Min
—
—
—
—
—
—
Typ
28
24
1.35
1.4
0.4
0.28
Max
70
86
3.0
3.1
1.0
0.71
Unit
ps
ps
ps
ps
ps
ps
RMS
GEN2
RMS
GEN3
RMS
GEN3_SRNS
RMS
GEN4
V
OX
V
HIGH
V
LOW
S
RNG
F
MOD
—
300
—
–0.3
0.4
—
—
—
–0.5
31.5
1.0
550
1.15
—
—
33
ps
mV
V
V
%
kHz
Down Spread, -B6 only
-B6 only
—
30
Notes:
1.
Visit
www.pcisig.com
for complete PCIe specifications.
2.
Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5
3.
Download the Silicon Labs PCIe Clock Jitter Tool at
www.silabs.com/pcie-learningcenter.
Rev 1.2
5
京公网安备 11010802033920号
EEWORLD
