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K9F1G08U0B
FLASH MEMORY
K9XXG08UXB
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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K9F1G08U0B
FLASH MEMORY
Document Title
128M x 8 Bit NAND Flash Memory
Revision History
Revision No
0.0
1.0
History
1. Initial issue
1. 1.8V device is eliminated
Draft Date
May 26. 2006
Sep. 27. 2006
Remark
Advance
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near your office.
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K9F1G08U0B
FLASH MEMORY
128M x 8 Bit NAND Flash Memory
PRODUCT LIST
Part Number
K9F1G08U0B-P
Vcc Range
2.70 ~ 3.60V
Organization
x8
PKG Type
TSOP1
FEATURES
•
Voltage Supply
- 3.3V Device(K9F1G08U0B) : 2.70V ~ 3.60V
•
Organization
- Memory Cell Array : (128M + 4M) x 8bit
- Data Register : (2K + 64) x 8bit
•
Automatic Program and Erase
- Page Program : (2K + 64)Byte
- Block Erase : (128K + 4K)Byte
•
Page Read Operation
- Page Size : (2K + 64)Byte
- Random Read : 25µs(Max.)
- Serial Access : 25ns(Min.)
•
Fast Write Cycle Time
- Page Program time : 200µs(Typ.)
- Block Erase Time : 1.5ms(Typ.)
•
Command/Address/Data Multiplexed I/O Port
•
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
•
Reliable CMOS Floating-Gate Technology
-Endurance : 100K Program/Erase Cycles(with 1bit/512Byte
ECC)
- Data Retention : 10 Years
•
Command Driven Operation
•
Intelligent Copy-Back with internal 1bit/528Byte EDC
•
Unique ID for Copyright Protection
•
Package :
- K9F1G08U0B-PCB0/PIB0 : Pb-FREE PACKAGE
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
GENERAL DESCRIPTION
Offered in 128Mx8bit, the K9F1G08U0B is a 1G-bit NAND Flash Memory with spare 32M-bit. Its NAND cell provides the most cost-
effective solution for the solid state application market. A program operation can be performed in typical 200µs on the (2K+64)Byte
page and an erase operation can be performed in typical 1.5ms on a (128K+4K)Byte block. Data in the data register can be read out
at 25ns cycle time per Byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip
write controller automates all program and erase functions including pulse repetition, where required, and internal verification and
margining of data. Even the write-intensive systems can take advantage of the K9F1G08U0B′s extended reliability of 100K program/
erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F1G08U0B is an optimum solu-
tion for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.
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K9F1G08U0B
PIN CONFIGURATION (TSOP1)
K9F1G08U0B-PCB0/PIB0
N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
FLASH MEMORY
48-pin TSOP1
Standard Type
12mm x 20mm
PACKAGE DIMENSIONS
48-PIN LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220F
Unit :mm/Inch
0.10
MAX
0.004
#48
( 0.25 )
0.010
12.40
0.488 MAX
0.50
0.0197
#24
#25
1.00
±0.05
0.039
±0.002
0.25
0.010 TYP
18.40
±0.10
0.724
±0.004
+0.075
20.00
±0.20
0.787
±0.008
0.008
-0.001
+0.07
+0.003
0.20
-0.03
#1
12.00
0.472
0.05
0.002 MIN
0.125
0.035
0~8°
0.45~0.75
0.018~0.030
( 0.50 )
0.020
4
0.005
-0.001
+0.003
1.20
0.047MAX
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K9F1G08U0B
PIN DESCRIPTION
Pin Name
I/O
0
~ I/O
7
Pin Function
FLASH MEMORY
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase operation.
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WRITE PROTECT
The WP pin provides inadvertent program/erase protection during power transitions. The internal high volt-
age generator is reset when the WP pin is active low.
READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
POWER
V
CC
is the power supply for device.
GROUND
NO CONNECTION
Lead is not internally connected.
CLE
ALE
CE
RE
WE
WP
R/B
Vcc
Vss
N.C
NOTE
: Connect all V
CC
and V
SS
pins of each device to common power supply outputs.
Do not leave V
CC
or V
SS
disconnected.
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