W523SXX
HIGH FIDELITY
GENERAL DESCRIPTION
(PRELIMINARY)
PowerSpeech
TM
The W523Sxx family are programmable speech synthesis ICs that utilize Winbond′s new high fidelity
voice synthesis algorithm to generate all types of voice effects with high sound quality.
The W523Sxx’ s LOAD, JUMP, MOVE and INC commands and ten programmable registers provide
powerful user-programmable functions that make this chip suitable for an extremely wide range of
speech IC applications.
The W523Sxx family includes 14 kinds of bodies which are the same except for the voice duration
shown below:
PART
NO.
Duration
PART
NO.
Duration
W523S08
8 sec.
W523S40
40 sec.
W523S10
10 sec.
W523S50
50 sec.
W523S12
12 sec.
W523S60
60 sec.
W523S15
15 sec.
W523S70
70 sec.
W523S20
20 sec.
W523S80
80 sec.
W523S25
25 sec.
W523S99
100 sec.
W523S30
30 sec.
W523M02
120 sec.
Note: The voice duration is estimated by 6.4 KHz sampling rate.
FEATURES
•
•
•
•
•
•
•
Operating voltage range: 2.4 – 5.5 volts for both DAC and PWM output
New high fidelity synthesis algorithm
Either PWM mode or D/A converter mode can be selected for AUD output
Provides 4 direct trigger inputs that can easily be extended to 24 matrix trigger inputs
Two trigger input debounce times (50 mS or 400 uS) can be set
Provides up to 2 LEDs and 5 STOP outputs
Flexible functions programmable through the following:
−
LD (Load), JP (Jump), MV (Move) and INC (Increase) commands
−
Four general purpose registers: R0, R1, R2 and R3
−
Six special purpose registers: EN0, EN1, MODE0, MODE1, STOP and PAGE
−
Conditional instructions: @LAST, @TGn_HIGH or LOW, where, n = 1,2,5 or 6
−
Speech equations
−
END instruction
•
•
•
•
Supports CPU interface operation
Symbolic compiler supported
Instruction cycle
≤
400
µS
typically
Section control for
−
Variable frequency: 4.8/6/8/12 KHz
Publication Release Date:Oct. 2000
Revision A5
-1-
W523SXX
−
LED: ON/OFF
•
(PRELIMINARY)
Up to 256 voice groups can be used in single page mode; or extended to 2,048 voice groups
in multi page mode, such as 8-page, 16-page and 32-page.
BLOCK DIAGRAM
OSC
TIMING GENERATOR
VDD1
RESET
TEST
TG1
TG2
TG5
TG6
VSS1
LED1
PWM DRIVER
D/A CONVERTER
CONTROLLER
SPEECH
SYNTHESIZER
ROM
STPA/BUSY
STPB
LED2/STPC
STPD
STPE
VSS2
VDD2
SPK+/AUD
SPK-
PIN DESCRIPTION
-2-
W523SXX
NAME
OSC
VDD1
TEST
RESET
(PRELIMINARY)
I/O
I
-
I
I
I
I
I
I
-
O
O
O
O
O
O
O
O
-
-
Ring oscillator input
Positive power supply
Test pin. Internally pulled low
DESCRIPTION
Active low to reset all devices as POR function. Internally pulled high.
Direct trigger input 1. Internally pulled high
Direct trigger input 2. Internally pulled high
Direct trigger input 5. Internally pulled high
Direct trigger input 6. Internally pulled high
Negative power supply
LED1 output
Stop signal A or Busy signal
Stop signal B
LED2 output or Stop signal C
Stop signal D
Stop signal E
PWM output
Current type output or PWM output for speaker
Negative power supply
Positive power supply
TG1
TG2
TG5
TG6
VSS1
LED1
STPA/BUSY
STPB
LED2/STPC
STPD
STPE
SPK-
AUD/SPK+
VSS2
VDD2
FUNCTIONAL DESCRIPTION
I/O pins:
The W523Sxx family provides up to 4 trigger pins, which can be extended to 24 matrix trigger inputs,
up to 5 STOP output pins and up to 2 LED output pins. All of these I/O pins’ status can be easily
defined by
PowerSpeech™
program.
Powerful programmable features:
The W523Sxx family provides JUMP (JP), LOAD (LD), MOVE (MV), INC, and END commands and 10
programmable registers, such as R0 ~ R3, EN0, EN1, MODE0, MODE1, STOP and PAGE, can be
easily used to program the desired playing mode, stop output signal form, LED flash type, and trigger
pin interrupt modes. The chip’ s programmable features can also be used to develop new, customized
functions for a wide variety of innovative applications.
Programmable Power-on Initialization:
Whenever the W523Sxx is powered on or pressed the
RESET
pin, the program contained in the 32
voice group will be executed after the power-on delay (about 160 mS), so the user can write a
program into this group to set the power-on initial state. If user does not wish to execute a program at
nd
-3-
Publication Release Date: Oct 2000
Revision A5
W523SXX
power-on, an “ END” instruction should be entered in the group 32.
(PRELIMINARY)
The interruption priority is shown as below while other trigger pins as well as JUMP (JP) command are
executing simultaneously during POI executing period:
POI > TG1F > TG1R > TG2F > TG2R > TG5F > TG5R > TG6F > TG6R > "JP" instruction.
Register Definition and Control
The register file in the W523Sxx family is composed of 10 registers, including 4 general-purpose
registers and 6 special purpose registers. They are defined to facilitate the operations for various
purposes. The default setting values of the registers are given in the following table.
REGISTER
General Register
Special Register
R0-R3
EN0
EN1
MODE0, MODE1
STOP
PAGE
NAME
DEFAULT SETTING
00100000B
XX11XX11B
XX11XX11B
11111111B
XXX11111B
00000000B
1.
MODE0 Register
BIT
7
6
4
2
DESCRIPTION
LED mode
LED2/STPC
pin selection
Debounce time
STPA/BUSY
pin selection
X
1: Flash
0: DC
1: LED2 output
0: STPC output
1: Long
0: Short
1: STPA output
0: BUSY output
Don’ t care
DEFINITION
5,3,1,0
The MODE0.7 bit defines the output type of LED1 and LED2 pins as Flash output (3 Hz) or DC output.
The MODE0.6 bit defines the configuration of LED2/STPC pin’ s status as LED2 output or STPC
output. The MODE0.4 bit defines the trigger pin’ s debounce time as long debounce (50 mS) or short
debounce (400 uS). The MODE0.2 bit defines the behavior of the STPA/BUSY pin as STPA output in
normal mode or BUSY signal output in CPU mode. The bits 5, 3, 1 and 0 are don’ t care bits.
-4-
W523SXX
(PRELIMINARY)
2.
MODE1 Register
BIT
7, 6, 1, 0
5
X
LED Flash type
DESCRIPTION
Don’ t care
1: Alternate
0: Synchronous
4
3
2
LED1 section
control
LED2 control
LED1 volume
control
1: YES
0: NO
1: SECTION control
0: STPC control
1: OFF
0: ON
DEFINITION
MODE1.5 is for LED flash type control. MODE1.4 is for LED1 section control ON/OFF. MODE1.3 is for
LED2 Section/STPC control. MODE1.2 is for LED1 volume control.
3.
PAGE Register
BIT
PAGE
-
7
-
6
-
5
4
PG4
3
PG3
2
PG2
1
PG1
0
PG0
The bits 0 ~ 4 in PAGE register are used for page selection. Once the page mode being defined
(referring to the below section of “Option Control Function”), the working page is selected by the bits 0
~ 4 in the PAGE register. Hence, the user can execute "LD PAGE, value" instruction to change the
working page of the voice entry group. Not all of the bits 0 ~ 4 of PAGE register are used in different
page mode. They are listed as below table:
PAGE MODE
1-page
8-page
16-page
32-page
PG4
×
×
×
√
PG3
×
×
√
√
PG2
×
√
√
√
PG1
×
√
√
√
PG0
×
√
√
√
Where "×" means don′t care and "√" means must be set properly.
4.
EN Register
BIT
EN0
EN1
7
X
X
6
X
X
5
TG2R
TG6R
4
TG1R
TG5R
3
X
X
2
X
X
1
TG2F
TG6F
0
TG1F
TG5F
EN0 or EN1 is an 8-bit register that stores the rising/falling edge enable or disable status information
for all trigger pins, which determines whether each trigger pin is retriggerable, non-retriggerable,
Publication Release Date: Oct 2000
Revision A5
-5-
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