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MT5C6401C-20L/IT

Description
Standard SRAM, 64KX1, 20ns, CMOS, CDIP22, DIP-22
Categorystorage    storage   
File Size129KB,10 Pages
ManufacturerMicross
Websitehttps://www.micross.com
Download Datasheet Parametric View All

MT5C6401C-20L/IT Overview

Standard SRAM, 64KX1, 20ns, CMOS, CDIP22, DIP-22

MT5C6401C-20L/IT Parametric

Parameter NameAttribute value
MakerMicross
Parts packaging codeDIP
package instructionDIP,
Contacts22
Reach Compliance Codecompliant
Maximum access time20 ns
Other featuresLG-MAX
JESD-30 codeR-CDIP-T22
length32.004 mm
memory density65536 bit
Memory IC TypeSTANDARD SRAM
memory width1
Number of functions1
Number of terminals22
word count65536 words
character code64000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize64KX1
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
width7.62 mm
Base Number Matches1
SRAM
Austin Semiconductor, Inc.
64K x 1 SRAM
SRAM MEMORY ARRAY
MT5C6401
PIN ASSIGNMENT
(Top View)
22-Pin DIP (C)
(300 MIL)
A0
A1
A2
A3
A4
A5
A6
A7
Q
WE\
Vss
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
Vcc
A15
A14
A13
A12
A11
A10
A9
A8
D
CE\
AVAILABLE AS MILITARY
SPECIFICATIONS
SMD 5962-86015
MIL-STD-883
FEATURES
• Speeds: 12, 15, 20, 25, 35, 45, 55, and 70ns
• Battery Backup: 2V data retention
• High-performance, low-power CMOS double-metal
process
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE\
• All inputs and outputs are TTL compatible
GENERAL DESCRIPTION
The Austin Semiconductor SRAM family employs
high-speed, low-power CMOS designs using a four-transistor
memory cell. Austin Semiconductor SRAMs are fabricated
using double-layer metal, double-layer polysilicon
technology.
For flexibility in high-speed memory applications, Austin
Semiconductor offers chip enable (CE\) on all organizations.
This enhancement can place the outputs in High-Z for
additional flexibility in system design. The X1 configuration
features separate data input and output.
Writing to these devices is accomplished when write
enable (WE\) and CE\ inputs are both LOW. Reading is
accomplished when WE\ remains HIGH and CE\ goes LOW.
The device offers a reduced power standby mode when
disabled. This allows system designs to achieve low standby
power requirements.
All devices operate from a single +5V power supply and
all inputs and outputs are fully TTL compatible.
OPTIONS
• Timing
12ns access
15ns access
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
• Package(s)
Ceramic DIP (300 mil)
MARKING
-12
-15
-20
-25
-35
-45*
-55*
-70*
C
No. 105
• Operating Temperature Ranges
Industrial (-40
o
C to +85
o
C)
IT
o
o
Military (-55 C to +125 C)
XT
• 2V data retention/low power
L
*Electrical characteristics identical to those provided for the 35ns
access devices.
For more products and information
please visit our web site at
www.austinsemiconductor.com
MT5C6401
Rev. 1.0 8/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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