FTA50DRES datasheet, PDF - EEWORLD Datasheet

FTA50DRES: DescriptionCard Edge Connector, 100 Contact(s), 2 Row(s), 0.125 inch Pitch, Hole .125-.137, Green Insulator; File Size433KB，3 Pages; ManufacturerSullins Connector Solutions

Download Datasheet Parametric View All

FTA50DRES Overview

Card Edge Connector, 100 Contact(s), 2 Row(s), 0.125 inch Pitch, Hole .125-.137, Green Insulator

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Objectid	1225725601
Reach Compliance Code	compliant
ECCN code	EAR99
YTEOL	0
Other features	NONE
body width	0.37 inch
subject depth	0.406 inch
body length	7.075 inch
Connector type	CARD EDGE CONNECTOR
Contactor design	PREASSEM CONN
Contact to complete cooperation	NOT SPECIFIED
Contact completed and terminated	Tin/Lead (Sn/Pb) - with Nickel (Ni) barrier
Contact material	NOT SPECIFIED
contact mode	RECTANGULAR
Contact resistance	10 mΩ
Contact style	BELLOWED TYPE
Dielectric withstand voltage	800VDC V
maximum insertion force	4.448 N
Insulation resistance	5000000000 Ω
Insulator color	GREEN
insulator material	POLYPHENYLENE SULFIDE
JESD-609 code	e0
Plug contact pitch	0.125 inch
Match contact row spacing	0.14 inch
Installation option 1	HOLE .125-.137
Installation option 2	HORIZONTAL DRILL
Number of rows loaded	2
Maximum operating temperature	200 °C
Minimum operating temperature	-65 °C
Plating thickness	100u inch
Rated current (signal)	3 A
Guideline	UL, CSA
Terminal length	0.225 inch
Total number of contacts	100
Maximum wire diameter	26 AWG
Evacuation force-minimum value	.278 N

Ask a question about extracting decimal numbers in verilog: I just recently learned that fpga uses verilog syntax. Now I have a question at hand. I have got a decimal number ex: 4913, and then I want to disassemble them into "4", "9", "1", " 3" and then conver...; eeleader FPGA/CPLD

Beaglebone peripheral circuit design experience sharing: For the use of OpenCV in this Beaglebone project, here is the installation method we have summarized. Those who are interested can refer to it and hope it is useful to everyone: [align=center]Opencv o...; PENGSHIFANG DSP and ARM Processors

Recruiting embedded software development engineers: Headhunting position [Hangzhou] Job responsibilities: 1. According to the company's needs, write the outline design document and detailed design document of embedded software; 2. According to the task...; ff318421749 Recruitment

Synplify Synthesis Problem: In synplify , I used the attribute property to locate some D flip-flops, but during the synthesis process, I found that all the D flip-flops with enable control were not located according to my constr...; eeleader FPGA/CPLD

msp463f5529 sampling ADC has no output: I use MSP430f5529 for ADC sampling. Why is there no output in ADC12MEM0? Passing by, please look here int main(void) { volatile unsigned int i; WDTCTL = WDTPW+WDTHOLD; // Stop watchdog timer P6SEL |= ...; jianhong0425 Microcontroller MCU

LC resonance: In Figure 8.1.16 of Tongshi Bai Model Electronics, 4th edition, P413, R is the total loss, but where is the load RL? Wasn't there a load RL on the N3 coil originally?...; msddw Analog electronics

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components