KAM21BR72A103MT datasheet, PDF

KAM21BR72A103MT: DescriptionCeramic Capacitor, Multilayer, Ceramic, 100V, 20% +Tol, 20% -Tol, X7R, 15% TC, 0.01uF, Surface Mount, 0805, CHIP; File Size838KB，7 Pages; ManufacturerAVX; Environmental Compliance

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KAM21BR72A103MT Overview

Ceramic Capacitor, Multilayer, Ceramic, 100V, 20% +Tol, 20% -Tol, X7R, 15% TC, 0.01uF, Surface Mount, 0805, CHIP

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Objectid	145640436786
package instruction	CHIP
Reach Compliance Code	compliant
ECCN code	EAR99
YTEOL	7
capacitance	0.01 µF
Capacitor type	CERAMIC CAPACITOR
dielectric materials	CERAMIC
high	0.94 mm
JESD-609 code	e2
length	2.01 mm
Installation features	SURFACE MOUNT
multi-layer	Yes
negative tolerance	20%
Number of terminals	2
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package form	SMT
method of packing	TR, PAPER, 7 INCH
positive tolerance	20%
Rated (DC) voltage (URdc)	100 V
Guideline	AEC-Q200
size code	0805
surface mount	YES
Temperature characteristic code	X7R
Temperature Coefficient	15% ppm/°C
Terminal surface	TIN NICKEL
Terminal shape	WRAPAROUND
width	1.25 mm

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

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