BX80525KY5002M/SL3CB datasheet, PDF

Datasheet> All Categories > BX80525KY5002M/SL3CB

BX80525KY5002M/SL3CB: DescriptionRISC Microprocessor, 32-Bit, 500MHz, CMOS; File Size2MB，112 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

Download Datasheet Parametric View All

BX80525KY5002M/SL3CB Overview

RISC Microprocessor, 32-Bit, 500MHz, CMOS

BX80525KY5002M/SL3CB Parametric

Parameter Name	Attribute value
Objectid	1164800047
package instruction	, SEC CARTRIDGE
Reach Compliance Code	unknown
YTEOL	0
bit size	32
Package body material	METAL
Encapsulate equivalent code	SEC CARTRIDGE
Certification status	Not Qualified
speed	500 MHz
technology	CMOS
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

Preview

Download Datasheet

View All

Pentium® III Xeon™ Processor at 500 and

550 MHz

Datasheet

Product Features

Binary compatible with applications

running on previous members of the Intel

microprocessor family

Optimized for 32-bit applications running

on advanced 32-bit operating systems

Dynamic Execution micro architecture

Dual Independent Bus architecture:

Separate dedicated external 100MHz

System Bus and dedicated internal cache

bus operating at full processor core speed

Power Management capabilities

— System Management mode

— Multiple low-power states

SMBus interface to advanced

manageability features

Intel

processor serial number

Single Edge Contact (S.E.C.) cartridge

packaging technology; the S.E.C. cartridge

delivers high performance processing and

bus technology in mid-range to high-end

servers and workstations

100 MHz system bus speeds data transfer

between the processor and the system

Integrated high performance16K

instruction and 16K data, nonblocking,

level-one cache

Available in 512K, 1 M, or 2 M unified,

nonblocking level-two cache

Enables systems which are scaleable up to

four processors and 64 GB of physical

memory

Streaming SIMD Extensions for enhanced

video, sound and 3D performance

The Intel® Pentium® III Xeon™ processor is designed for mid-range to high-end servers and workstations, and is binary

compatible with previous Intel Architecture processors. The Pentium III Xeon processor provides the best performance

available for applications running on advanced operating systems such as Windows* 95, Windows NT, and UNIX*. The

Pentium III Xeon processor is scalable to four processors in a multiprocessor system and extends the power of the

Pentium® Pro processor with new features designed to make this processor the right choice for powerful workstation,

advanced server management, and mission-critical applications. Pentium III Xeon processor-based workstations offer

the memory architecture required by the most demanding workstation applications and workloads. Specific features of

the Pentium III Xeon processor address platform manageability to meet the needs of a robust IT environment, maximize

system up time and ensure optimal configuration and operation of servers. The Pentium III Xeon processor enhances the

ability of server platforms to monitor, protect, and service the processor and its environment.

Order Number: 245094-002

February 2000

Pentium

III Xeon™ Processor at 500 and 550 MHz

Contents

1.0

Introduction.........................................................................................................................9

1.1

1.2

2.0

2.1

2.2

2.3

Terminology...........................................................................................................9

1.1.1 S.E.C. Cartridge Terminology ................................................................10

References ..........................................................................................................10

The Pentium

III Xeon™ Processor System Bus and V

REF

...............................11

Power and Ground Pins ......................................................................................12

Decoupling Guidelines ........................................................................................12

2.3.1 Pentium

III Xeon™ Processor V

CCCORE

..............................................13

2.3.2 Level 2 Cache Decoupling .....................................................................13

2.3.3 System Bus AGTL+ Decoupling.............................................................13

System Bus Clock and Processor Clocking ........................................................13

2.4.1 Mixing Processors ..................................................................................15

Voltage Identification ...........................................................................................16

System Bus Unused Pins and Test Pins.............................................................17

System Bus Signal Groups .................................................................................18

2.7.1 Asynchronous vs. Synchronous for System Bus Signals.......................19

Test Access Port (TAP) Connection....................................................................19

Maximum Ratings................................................................................................20

Processor DC Specifications...............................................................................20

AGTL+ System Bus Specifications .....................................................................24

System Bus AC Specifications ............................................................................25

System Bus Clock Signal Quality Specifications.................................................33

AGTL+ Signal Quality Specifications ..................................................................33

3.2.1 AGTL+ Ringback Tolerance Specifications............................................34

3.2.2 AGTL+ Overshoot/Undershoot Guidelines.............................................34

Non-AGTL+ Signal Quality Specifications...........................................................35

3.3.1 2.5 V Tolerant Buffer Overshoot/Undershoot Guidelines .......................35

3.3.2 2.5 V Tolerant Buffer Ringback Specification.........................................35

3.3.3 2.5 V Tolerant Buffer Settling Limit Guideline ........................................36

Functional Redundancy Checking Mode.............................................................36

Low Power States and Clock Control..................................................................37

4.2.1 Normal State— State 1 ..........................................................................37

4.2.2 Auto Halt Power Down State — State 2 .................................................37

4.2.3 Stop-Grant State — State 3 ...................................................................38

4.2.4 Halt/Grant Snoop State — State 4 .........................................................39

4.2.5 Sleep State — State 5............................................................................39

4.2.6 Clock Control..........................................................................................39

System Management Bus (SMBus) Interface .....................................................40

4.3.1 Processor Information ROM...................................................................41

4.3.2 Scratch EEPROM...................................................................................42

Electrical Specifications....................................................................................................11

2.4

2.5

2.6

2.7

2.8

2.9

2.10

2.11

2.12

3.0

3.1

3.2

Signal Quality ...................................................................................................................32

3.3

4.0

Processor Features ..........................................................................................................36

4.1

4.2

4.3

Datasheet

Pentium

III Xeon™ Processor at 500 and 550 MHz

4.3.3

4.3.4

4.3.5

4.3.6

4.3.7

5.0

5.1

Processor Information ROM and Scratch EEPROM Supported

SMBus Transactions ..............................................................................43

Thermal Sensor......................................................................................43

Thermal Sensor Supported SMBus Transactions..................................44

Thermal Sensor Registers......................................................................46

4.3.6.1 Thermal Reference Registers ................................................... 46

4.3.6.2 Thermal Limit Registers ............................................................46

4.3.6.3 Status Register..........................................................................46

4.3.6.4 Configuration Register...............................................................47

4.3.6.5 Conversion Rate Register .........................................................47

SMBus Device Addressing.....................................................................48

Thermal Specifications and Design Considerations.........................................................49

Thermal Specifications........................................................................................50

5.1.1 Power Dissipation ..................................................................................50

5.1.2 Plate Flatness Specification ...................................................................51

Processor Thermal Analysis ...............................................................................51

5.2.1 Thermal Solution Performance...............................................................51

5.2.2 Thermal Plate to Heat Sink Interface Management Guide..................... 52

5.2.3 Measurements for Thermal Specifications............................................. 53

5.2.3.1 Thermal Plate Temperature Measurement ............................... 53

5.2.3.2 Cover Temperature Measurement Guideline ............................ 54

Weight .................................................................................................................60

Cartridge to Connector Mating Details ................................................................60

Pentium

III Xeon™ Processor Substrate Edge Finger Signal Listing ............... 62

Introduction .........................................................................................................71

Mechanical Specifications...................................................................................71

7.2.1 Boxed Processor Heatsink Dimensions ................................................. 73

7.2.2 Boxed Processor Heatsink Weight.........................................................73

7.2.3 Boxed Processor Retention Mechanism ................................................ 73

Thermal Specifications........................................................................................74

7.3.1 Boxed Processor Cooling Requirements ...............................................74

7.3.2 Optional Auxiliary Fan Attachment .........................................................74

7.3.2.1 Clearance Recommendations for Auxiliary Fan ........................ 76

7.3.2.2 Fan Power Recommendations for Auxiliary Fan ....................... 77

7.3.2.3 Thermal Evaluation for Auxiliary Fan ........................................ 78

In-Target Probe (ITP) for Pentium

III Xeon™ Processors................................. 78

8.1.1 Primary Function ....................................................................................79

8.1.2 Debug Port Connector Description.........................................................79

8.1.3 Debug Port Signal Descriptions .............................................................80

8.1.4 Debug Port Signal Notes........................................................................82

8.1.4.1 General Signal Quality Notes .................................................... 83

8.1.4.2 Signal Note: DBRESET#...........................................................83

8.1.4.3 Signal Note: TDO and TDI ........................................................83

8.1.4.4 Signal Note: TCK.......................................................................83

8.1.5 Using Boundary Scan to Communicate to the Processor ...................... 85

5.2

6.0

Mechanical Specifications................................................................................................55

6.1

6.2

6.3

7.0

Boxed Processor Specifications.......................................................................................71

7.1

7.2

7.3

8.0

Integration Tools ..............................................................................................................78

8.1

Datasheet

Pentium

III Xeon™ Processor at 500 and 550 MHz

8.2

9.0

9.1

Integration Tool (Logic Analyzer) Considerations ...............................................86

Alphabetical Signals Reference ..........................................................................86

9.1.1 A[35:03]# (I/O)........................................................................................86

9.1.2 A20M# (I)................................................................................................86

9.1.3 ADS# (I/O)..............................................................................................87

9.1.4 AERR# (I/O) ...........................................................................................87

9.1.5 AP[1:0]# (I/O) .........................................................................................87

9.1.6 BCLK (I)..................................................................................................87

9.1.7 BERR# (I/O) ...........................................................................................87

9.1.8 BINIT# (I/O) ............................................................................................88

9.1.9 BNR# (I/O)..............................................................................................88

9.1.10 BP[3:2]# (I/O) .........................................................................................88

9.1.11 BPM[1:0]# (I/O) ......................................................................................88

9.1.12 BPRI# (I).................................................................................................88

9.1.13 BR0# (I/O), BR[3:1]# (I) ..........................................................................88

9.1.14 CPU_SENSE..........................................................................................89

9.1.15 D[63:00]# (I/O)........................................................................................89

9.1.16 DBSY# (I/O) ...........................................................................................90

9.1.17 DEFER# (I).............................................................................................90

9.1.18 DEP[7:0]# (I/O).......................................................................................90

9.1.19 DRDY# (I/O) ...........................................................................................90

9.1.20 EMI .........................................................................................................90

9.1.21 FERR# (O) .............................................................................................90

9.1.22 FLUSH# (I) .............................................................................................90

9.1.23 FRCERR (I/O) ........................................................................................91

9.1.24 HIT# (I/O), HITM# (I/O) ..........................................................................91

9.1.25 IERR# (O)...............................................................................................91

9.1.26 IGNNE# (I)..............................................................................................91

9.1.27 INIT# (I) ..................................................................................................92

9.1.28 INTR - see LINT0 ...................................................................................92

9.1.29 LINT[1:0] (I) ............................................................................................92

9.1.30 LOCK# (I/O) ...........................................................................................92

9.1.31 L2_SENSE .............................................................................................93

9.1.32 NMI - See LINT1 ....................................................................................93

9.1.33 PICCLK (I) ..............................................................................................93

9.1.34 PICD[1:0] (I/O)........................................................................................93

9.1.35 PM[1:0]# (O) ...........................................................................................93

9.1.36 PRDY# (O) .............................................................................................93

9.1.37 PREQ# (I)...............................................................................................93

9.1.38 PWREN[1:0] (I).......................................................................................93

9.1.39 PWRGOOD (I)........................................................................................93

9.1.40 REQ[4:0]# (I/O) ......................................................................................94

9.1.41 RESET# (I) .............................................................................................94

9.1.42 RP# (I/O) ................................................................................................95

9.1.43 RS[2:0]# (I) .............................................................................................95

9.1.44 RSP# (I)..................................................................................................95

9.1.45 SA[2:0] (I) ...............................................................................................95

9.1.46 SELFSB[1:0] (I/O) ..................................................................................96

Appendix ..........................................................................................................................86

Datasheet

Recommended Resources

Tropical fish tank water temperature automatic controller circuit diagram

Wiring d when leakage protector supplies power to single-phase load in TN system

Circuit diagram of an integrator AC-coupled with a junction field effect transistor

Buck regulator circuit diagram using LM2579

4-20mA transmitter circuit using MPX7100 pressure sensor

Wien bridge sine wave oscillator circuit

[An analog circuit has defeated many heroes, looking forward to experts] Can you tell me about the band-stop filter on this website?: First I'll post the circuit diagram. Haha, the transfer function of this circuit I simulated in pspice is quite normal. I don't know why, but when I actually built a circuit (op4558 dual power supply ...; huayang1118 Analog electronics

Anyone who has done Kickstarter crowdfunding need advice?: I would like to ask about the process and details of crowdfunding on Kickstarter, such as registration, initiation, export, mailing, patent, and after-sales. Has anyone done this and can you give me s...; littleshrimp Integrated technical exchanges

ADS1248 constant current source has no output, it turns out this is the reason: [i=s] This post was last edited by littleshrimp on 2017-8-28 16:53 [/i] ADS1248 uses a constant current source to measure RTD (PT100). After all configurations are completed, it is found that there is...; littleshrimp Test/Measurement

AD sampling trigger mode setting problem: At present, the original program already contains an ad sampling program, the trigger mode is PWM event, the sampling sequence is 0, and it is mainly used to obtain the current and voltage of the runn...; highbury2006 Microcontroller MCU

About the interface between BT835 video decoding chip and FPGA: I hope that forum friends can give me some advice on how to read video data from FPGA. This is my first time to deal with video processing and I am completely confused! I have read some information in...; 电子亮晶晶 FPGA/CPLD

Please give me some advice. I want to generate a PWM wave with a duty cycle of 25%. The error message generated by Keil compilation and connection is as follows: Generate a PWM wave with a duty cycle of 25%. Use Keil to compile and connect. Error information is generated as shown in the color below: ORG 0000H LJMP MAIN ORG 000BH LJMP T0INT ORG 001BH LJMP T1INT...; wangtong0819 Embedded System

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components