P
RELIMINARY
P
RODUCT
S
PECIFICATION
1
Z89321/371/391
16-B
IT
D
IGITAL
S
IGNAL
P
ROCESSORS
FEATURES
Device
Z89321
Z89371
Z89391
Note:
*External
s
1
DSP ROM
(KW)
4
OTP
(KW)
4
DSP RAM
Lines
512
512
512
MIPS
(Max)
24
16
24
Device
Z89321
Z89371
Z89391
40-Pin
DIP
X
X
44-Pin
PLCC
X
X
44-Pin
QFP
X
X
84-Pin
PLCC
64*
X
Note:
*General-Purpose
0
°
C to +70
°
C Standard Temperature Range
-40
°
C to +85
°
C Extended Temperature Range
4.5- to 5.5-Volt Operating Range
On-Board Peripherals
s
s
Dual 8/16-Bit CODEC Interface Capable of up to
10 Mbps
m
-Law Compression Option
(Decompression is Performed in Software)
16-Bit I/O Bus (Tri-Stated)
Three I/O Address Pins (Latched Outputs)
Wait-State Generator
Three Vectored Interrupts
13-Bit General-Purpose Timer
DSP Core
s
s
s
s
s
s
24 MIPS @ 24 MHz Maximum, 16-Bit Fixed Point DSP
s
41.7 ns Minimum Instruction Cycle Time
s
Six-Level Hardware Stack
s
Six Register Address Pointers
s
Optimized Instruction Set (30 Instructions)
s
GENERAL DESCRIPTION
The Z893XX products are high-performance Digital Signal
Processors (DSPs) with a modified Harvard-type architec-
ture featuring separate program and data memory. The de-
sign has been optimized for processing power while mini-
mizing silicon space.
The single-cycle instruction execution and bus structure
promotes efficient algorithm execution, while the six regis-
ter pointers provide circular buffering capabilities and dual
operand fetching.
Three vectored interrupts are complemented by a six-level
stack, and the CODEC interface allows high-speed trans-
fer rates to accommodate digital audio and voice data.
A dedicated Counter/Timer provides the necessary timing
signals for the CODEC interface, and an additional 13-bit
timer is available for general-purpose use.
DS97DSP0100
PRELIMINARY
1
Z89321/371/391
16-Bit Digital Signal Processors
The Z893XX DSPs are optimized to accommodate ad-
vanced signal processing algorithms. The 24 MIPS (maxi-
mum) operating performance and efficient architecture
provides real-time instruction execution. Compression, fil-
tering, frequency detection, audio, voice detection/synthe-
sis, and other vital algorithms can all be accommodated.
The Z89321/371/391 devices feature an on-board CO-
DEC interface, compatible with 8-bit PCM and 16-bit CO-
DECs for digital audio applications. Additionally, an on-
board wait-state generator is provided to accommodate
slow external peripherals.
For prototypes, as well as production purposes, the
Z89371 member of the DSP product family is a one-time
Zilog
pro-grammable (OTP) device with a 16 MHz maximum op-
erating frequency.
Notes:
All signals with a preceding front slash, "/", are
active Low. For example, B//W (WORD is active Low);
/B/W (BYTE is active Low, only).
Power connections follow conventional descriptions be-
low:
Connection
Power
Ground
Circuit
V
CC
GND
Device
V
DD
V
SS
Program
ROM/OTP
4096x16
PA0-15
PD0-15
PDATA
PADDR
Data RAM0
256x16
Data RAM1
256x16
DDAT
A
EA0-2
EXT0-15
/DS
WAIT
RD//WR
XDAT
A
P0
X
Y
P1
P2
DP0-3
ADDR
GEN0
P0
P1
P2
DP4-6
ADDR
GEN1
8/16-Bit,
Full Duplex,
10 MBPS
Serial Port
Multiplier
INT0-2
HALT
/RESET
CLK
Program
Control
Unit
P
Shifter
TXD
RXD
SCLK
FS0
FS1
13-Bit Timer
User I/O
UI1-0
UO1-0
Arithmetic
Logic Unit
(ALU)
Accumulator
Figure 1. Z89321/371/391 Functional Block Diagram
2
PRELIMINARY
DS97DSP0100
Zilog
Z89321/371/391
16-Bit Digital Signal Processors
PIN DESCRIPTION
EXT12
EXT13
EXT14
VSS
EXT15
EXT3
EXT4
VSS
EXT5
EXT6
EXT7
TXD
EXT8
EXT9
VSS
EXT10
EXT11
UI1
UI0
SCLK
1
40
DIP 40 - Pin
20
21
RXD
VSS
EXT2
EXT1
EXT0
VSS
FS1
U01
U00
/INT0
FS0
CLK
/DS
VDD
EA2
EA1
EA0
/RESET
RD//WR
VDD
1
Figure 2. Z89321/371 40-Pin DIP Pin Assignments
Table 1. Z89321/371 40-Pin DIP Pin IdentiÞcation
No.
1-3
4
5
6-7
8
9-11
12
13-14
15
16-17
18
19
20
21
22
Symbol
EXT12-
EXT14
V
SS
EXT15
Function
External Data
Bus
Ground
Direction
Input/Output
Table 1. Z89321/371 40-Pin DIP Pin IdentiÞcation
No.
23
24-26
27
28
Input/Output
29
30
Input/Output
Output
Input/Output
35
36-38
Input/Output
39
Input
Input
Input/Output*
Input
Output
40
V
SS
31
32-33
34
/INT0
UO0-UO1
FS1
CLK
FS0
Symbol
/RESET
EA0-EA2
V
DD
/DS
Function
Direction
External Data
Bus
EXT3-EXT4 External Data
Bus
V
SS
Ground
EXT5-EXT7 External Data
Bus
TXD
Serial Output to
CODECs
EXT8-EXT9 External Data
Bus
V
SS
Ground
EXT10-
EXT11
UI1
UI0
SCLK
V
DD
RD//WR
External Data
Bus
User Input
User Input
CODEC Serial
Clock
Power Supply
Strobes for
External Bus
Input/Output
Reset
Input
External Address Output
Bus
Power Supply
Input
Data Strobe for
External Bus
Clock
CODEC 0 Frame
Sync
Interrrupt
User Output
CODEC 1 Frame
Sync
Ground
Output
Input
Input/Output*
Input
Output
Input/Output*
EXT0-EXT2 External Data
Bus
V
SS
Ground
RXD
Input/Output
Serial Input from Input
CODECs
Notes:
*Input/Output is defined by interface mode selection.
HALT/WAIT pins not available on 40-pin DIP package.
DS97DSP0100
PRELIMINARY
3
Z89321/371/391
16-Bit Digital Signal Processors
Zilog
PIN DESCRIPTION
(Continued)
VSS
EXT0
EXT1
EXT2
VSS
RXD
EXT12
EXT13
EXT14
VSS
EXT15
7
FS1
UO1
UO0
/INT0
FSO
HALT
CLK
/DS
VDD
EA2
EA1
6
1
40
39
PLCC 44 -Pin
17
18
29
28
EA0
/RESET
WAIT
RD//WR
VDD
SCLK
UI0
UI1
INT1
INT2
EXT11
Figure 3. Z89321/371 44-Pin PLCC Pin Assignments
4
EXT3
EXT4
VSS
EXT5
EXT6
EXT7
TXD
EXT8
EXT9
VSS
EXT10
PRELIMINARY
DS97DSP0100
Zilog
Z89321/371/391
16-Bit Digital Signal Processors
Table 2. Z89321/371 44-Pin PLCC Pin IdentiÞcation
No.
1
2
3
4-5
6
7
8-10
11
12
13-15
16
17
18-19
20
21-23
24
25-26
27
28-29
30
31
32
33
34
35
36
37
38
39-41
42
43
44
Symbol
HALT
FS0
/INT0
O0-UO1
FS1
V
SS
EXT0-EXT2
V
SS
RXD
EXT12-EXT14
V
SS
EXT15
EXT3-EXT4
V
SS
EXT5-EXT7
TXD
EXT8-EXT9
V
SS
EXT10-EXT11
/INT2
/INT1
UI1
UI0
SCLK
V
DD
RD//WR
WAIT
/RESET
EA0-EA2
V
DD
/DS
CLK
Function
Stop Execution
CODEC 0 Frame Sync
Interrupt
User Output
CODEC 1 frame sync
Ground
External data bus
Ground
Serial input from CODECs
External data bus
Ground
External data bus
External data bus
Ground
External data bus
Serial output to CODECs
External data bus
Ground
External data bus
Interrupt
Interrupt
User input
User input
CODEC serial clock
Power supply
RD//WR strobe for EXT bus
WAIT state
Reset
External Address bus
Power Supply
Data strobe for external bus
Clock
Direction
Input
Input/Output*
Input
Output
Input/Output*
Input/Output
Input
Input/Output
Input/Output
Input/Output
Input/Output
Output
Input/Output
Input/Output
Input
Input
Input
Input
Input/Output*
Input
Output
Input
Input
Output
Input
Output
Input
1
Note:
* Input or output is defined by interface mode selection.
DS97DSP0100
PRELIMINARY
5
京公网安备 11010802033920号
EEWORLD
