EEWORLDEEWORLDEEWORLD

Part Number

Search

PT7V4050GATHA16.384/12.500

Description
PLL/Frequency Synthesis Circuit,
CategoryAnalog mixed-signal IC    The signal circuit   
File Size156KB,7 Pages
ManufacturerDiodes Incorporated
Download Datasheet Parametric View All

PT7V4050GATHA16.384/12.500 Overview

PLL/Frequency Synthesis Circuit,

PT7V4050GATHA16.384/12.500 Parametric

Parameter NameAttribute value
Objectid4000508738
package instructionSON,
Reach Compliance Codecompliant
ECCN codeEAR99
YTEOL0
Analog Integrated Circuits - Other TypesPHASE DETECTOR
JESD-30 codeR-PDSO-N16
length20.32 mm
Number of functions1
Number of terminals16
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSON
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Maximum seat height4.15 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal formNO LEAD
Terminal pitch2.54 mm
Terminal locationDUAL
width10.16 mm
Data Sheet
PT7V4050
PLL with quartz stabilized VCXO
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Features
PLL with quartz stabilized VCXO
Loss of signals alarm
Return to nominal clock upon LOS
Input data rates from 8 kb/s to 65 Mb/s
Tri-state output
User defined PLL loop response
NRZ data compatible
Single +5.0V power supply
Description
The device is composed of a phase-lock loop with an
integrated VCXO for use in clock recovery, data re-
timing, frequency translation and clock smoothing
applications in telecom and datacom systems.
Crystal Frequencies Supported: 12.000~50.000 MHz.
Block Diagram
CLKIN
DATAIN
HIZ
Phase Detector &
Loss Of Signal
Circuit
RCLK
RDATA
LOS
PHO
VC
LOSIN
CLK1
VCXO
Divider
CLK2
OPN
Op
Amp
OPOUT
OPP
Ordering Information
PT7V4050
Device Type
16-pin clock recoverymodule
PackageLeads
T: Thru-Hole
G: Surface Mount
CLK2 Divider
A: Divide by 2 E: Divide by 32
B: Divide by 4 F: Divide by 64
C: Divide by 8 G: Divide by 128
D: Divide by 16 H: Divide by 256
K: Disable
T
B
C
G
A
49.408 / 12.352
CLK2 Frequency
CLK1 Frequency
A: 5.0V supply voltage
B: 3.3V supply voltage
C:
±
20ppm
F:
±
32ppm
G:
±
50ppm
H:
±
100ppm
Temperature Range
C: 0
°
C to 70
°
C
T: -40
°
C to 85
°
C
12.000
16.128
18.432
22.579
28.000
34.368
44.736
Frequencies using at CLK1 (MHz)
12.288
12.624
13.00
16.384
16.777
16.896
18.936
20.000
20.480
24.576
24.704
25.000
30.720
32.000
32.768
38.880
40.000
41.2416
47.457
49.152
49.408
19.440
35.328
16.000
17.920
22.1184
27.000
33.330
41.943
50.000
40.960
Note:
CLK1 up to 40.960MHz for both 5V and
3.3V for temperature -40oC to 85 oC; CLK1 up to
50MHz for both 5V and 3.3V for temperature 0oC to 70oC.
PT0125(02/06)
1
Ver:2
Vehicle-mounted card reader solution
Our company now launches a car card reader board solution, which can support a variety of cards (SD, MMC, MS, XD), with USB. If you need it, please contact QQ: 77964937 Mobile 13923792063 Mr. Xia...
jordanzhen23 Automotive Electronics
【Yang Gong Column】LED Street Light Driving Circuit Technology
The 2010 training course on "Energy-saving Technology for Road Lighting and Tunnel Lighting" includes: LED green lighting fixtures; the main market for high-brightness LED drivers; the working princip...
颜工 Power technology
42-inch LCD TVs fall below 10,000 yuan for the first time, flat-panel TVs are unlikely to sell at sky-high prices
[i=s]This post was last edited by jameswangsynnex on 2015-3-3 19:59[/i] As flat-panel TV manufacturers repeatedly said that there was no room for price cuts, home appliance stores were not worried abo...
Felix Mobile and portable
Bad jokes
In English class, the teacher said: "Your English is so bad that I can't understand you at all."...
zxh5409 Talking
DSP from entry to mastery complete collection
DSP from entry to mastery complete collection...
设计王者 DSP and ARM Processors
Three common buses [reprint]
[i=s]This post was last edited by caicaiwoshishui on 2015-10-31 22:31[/i] [p=35, null, left][color=#555555]Embedded system is a hot spot in the development of computer industry. With the rapid develop...
caicaiwoshishui FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2249  2454  2919  1025  1293  46  50  59  21  27 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号