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CBTD3306
Dual bus switch with level shifting
Rev. 8 — 1 May 2012
Product data sheet
1. General description
The CBTD3306 dual FET bus switch features independent line switches. Each switch is
disabled when the associated output enable (nOE) input is HIGH.
The CBTD3306 is characterized for operation from
−40 °C
to +85
°C.
2. Features and benefits
Designed to be used in 5 V to 3.3 V level shifting applications with internal diode
5
Ω
switch connection between two ports
TTL-compatible input levels
Multiple package options
Latch-up protection exceeds 100 mA per JESD78B
ESD protection:
HBM JESD22-A114F exceeds 2000 V
CDM JESD22-C101E exceeds 1000 V
3. Ordering information
Table 1.
Ordering information
Package
Name
CBTD3306D
CBTD3306PW
CBTD3306GT
CBTD3306GM
SO8
TSSOP8
XSON8
XQFN8
Description
plastic small outline package; 8 leads; body width 3.9 mm
plastic thin shrink small outline package; 8 leads;
body width 4.4 mm
plastic extremely thin small outline package; no leads; 8 terminals;
body 1
×
1.95
×
0.5 mm
plastic, extremely thin quad flat package; no leads; 8 terminals;
body 1.6
×
1.6
×
0.5 mm
Version
SOT96-1
SOT530-1
SOT833-1
SOT902-2
Type number
4. Marking
Table 2.
Marking codes
Marking code
CBD3306
D306
W06
W06
Type number
CBTD3306D
CBTD3306PW
CBTD3306GT
CBTD3306GM
NXP Semiconductors
CBTD3306
Dual bus switch with level shifting
5. Functional diagram
2
1
5
7
002aab985
1A
1OE
2A
2OE
3
1B
6
2B
Fig 1.
Logic diagram
6. Pinning information
6.1 Pinning
CBTD3306
CBTD3306
1OE
1A
1B
GND
1
2
3
4
001aak832
8
7
6
5
V
CC
2OE
2B
2A
1OE
1A
1B
GND
1
2
3
4
001aak833
8
7
6
5
V
CC
2OE
2B
2A
Fig 2.
Pin configuration for SO8 (SOT96-1)
Fig 3.
Pin configuration for TSSOP8 (SOT530-1)
CBTD3306
CBTD3306
1OE
1
8
V
CC
terminal 1
index area
1OE
1
V
CC
8
7
2OE
1A
2
7
2OE
1A
2
6
2B
1B
3
6
2B
1B
3
4
5
2A
GND
GND
4
5
2A
001aal405
001aal404
Transparent top view
Transparent top view
Fig 4.
Pin configuration SOT833-1 (XSON8)
Fig 5.
Pin configuration SOT902-2 (XQFN8)
CBTD3306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 8 — 1 May 2012
2 of 17
NXP Semiconductors
CBTD3306
Dual bus switch with level shifting
6.2 Pin description
Table 3.
Symbol
1OE, 2OE
1A, 2A
1B, 2B
GND
V
CC
Pin description
Pin
1, 7
2, 5
3, 6
4
8
Description
output enable input
data input/output (A port)
data input/output (B port)
ground (0 V)
positive supply voltage
7. Functional description
Table 4.
Input
nOE
L
H
[1]
Function selection
[1]
Input/output
nA, nB
nA = nB
Z
H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
[1]
T
amb
=
−
40
°
C to +85
°
C, unless otherwise specified.
Symbol
V
CC
V
I
I
SW
I
IK
T
stg
[1]
Parameter
supply voltage
input voltage
switch current
input clamping current
storage temperature
Conditions
[2]
Min
−0.5
−0.5
-
−50
−65
Max
+7.0
+7.0
128
-
+150
Unit
V
V
mA
mA
°C
V
I/O
= 0 V
Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under
Section 9.
is not implied. Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
[2]
9. Recommended operating conditions
Table 6.
Operating conditions
All unused control inputs of the device must be held at V
CC
or GND to ensure proper device operation.
Symbol
V
CC
V
IH
V
IL
T
amb
Parameter
supply voltage
HIGH-level input voltage
LOW-level input voltage
ambient temperature
operating in free air
Conditions
Min
4.5
2.0
-
−40
Typ
-
-
-
-
Max
5.5
-
0.8
+85
Unit
V
V
V
°C
CBTD3306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 8 — 1 May 2012
3 of 17
NXP Semiconductors
CBTD3306
Dual bus switch with level shifting
10. Static characteristics
Table 7.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol
V
IK
I
I
I
CC
V
pass
ΔI
CC
Parameter
input clamping voltage
input leakage current
supply current
pass voltage
additional supply current
Conditions
V
CC
= 4.5 V; I
I
=
−18
mA
V
CC
= 5.5 V; V
I
= GND or 5.5 V
V
CC
= 5.5 V; I
SW
= 0 mA;
V
I
= V
CC
or GND
see
Figure 6
to
Figure 10
per input pin; V
CC
= 5.5 V;
one input at 3.4 V, other inputs at
V
CC
or GND
control pin; V
I
= 3 V or 0 V
port off; V
I
= 3 V or 0 V; nOE = V
CC
V
CC
= 4.5 V; V
I
= 0 V; I
I
= 64 mA
V
CC
= 4.5 V; V
I
= 0 V; I
I
= 30 mA
V
CC
= 4.5 V; V
I
= 2.4 V; I
I
= 15 mA
[1]
[2]
[3]
All typical values are at V
CC
= 5 V, T
amb
= 25
°C.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
CC
or GND.
Measured by the voltage drop between the nA and the nB terminals at the indicated current through the switch. ON resistance is
determined by the lowest voltage of the two (nA or nB) terminals.
[3]
[3]
[3]
[2]
T
amb
=
−40 °C
to +85
°C
Min
-
-
-
-
-
Typ
[1]
-
-
-
-
-
Max
−1.2
±1
1.5
-
2.5
Unit
V
μA
mA
V
mA
C
I
C
io(off)
R
ON
input capacitance
off-state input/output
capacitance
ON resistance
-
-
-
-
-
3.2
6.5
3.6
3.6
17
-
-
5
5
35
pF
pF
Ω
Ω
Ω
CBTD3306
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 8 — 1 May 2012
4 of 17
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