54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop
54F/74F109
November 1994
54F/74F109
Dual JK Positive Edge-Triggered Flip-Flop
General Description
The ’F109 consists of two high-speed, completely indepen-
dent transition clocked JK flip-flops. The clocking operation
is independent of rise and fall times of the clock waveform.
The JK design allows operation as a D flip-flop (refer to ’F74
data sheet) by connecting the J and K inputs.
Asynchronous Inputs:
LOW input to S
D
sets Q to HIGH level
LOW input to C
D
sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes both Q and Q
HIGH
Features
Ordering Code:
Commercial
74F109PC
74F109SC (Note 1)
74F109SJ (Note 1)
See Section 0
Military
te
n
Guaranteed 4000V minimum ESD protection.
Package Description
16-Lead (0.300" Wide) Molded Dual-in-Line
16-Lead Ceramic Dual-in-Line
16-Lead (0.150" Wide) Molded Small Outline,
JEDEC
16-Lead (0.300" Wide) Molded Small Outline,
EIAJ
16-Lead Cerpack
16-Lead Ceramic Leadless Chip Carrier, Type C
IEEE/IEC
DS009471-6
DSXXX
Package
Number
N16E
J16A
54F109DM (Note 2)
O
bs
o
54F109LM (Note 2)
E20A
Note 1:
Devices also available in 13" reel. Use suffix = SCX and SJX.
54F109FM (Note 2)
Note 2:
Military grade device with environmental and burn-in processing. Use suffix = DMQB, FMQB and LMQB.
Logic Symbols
DS009471-3
FAST
®
and TRI-STATE
®
are registered trademarks of National Semiconductor Corporation.
le
M16A
M16D
W16A
DS009471-4
© 1997 National Semiconductor Corporation
DS009471
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Proof
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Connection Diagrams
Pin Assignment
for DIP, SOIC and Flatpak
Pin Assignment
for LCC
DS009471-1
DS009471-2
See Section 0 for U.L. definitions
Pin Names
J
1
, J
2
, K
1
, K
2
CP
1
, CP
2
C
D1
, C
D2
S
D1
, S
D2
Q
1
, Q
2
, Q
1
, Q
2
Data Inputs
Direct Clear Inputs (Active LOW)
Direct Set Inputs (Active LOW)
Outputs
Description
te
54F/74F
U.L.
Input I
IH
/I
IL
HIGH/LOW
1.0/1.0
1.0/1.0
Output I
OH
/I
OL
20 µA/−0.6 mA
20 µA/−0.6 mA
1.0/3.0
1.0/3.0
20 µA/−1.8 mA
20 µA/−1.8 mA
−1 mA/20 mA
50/33.3
2
Unit Loading/Fan Out
DSXXX
Clock Pulse Inputs (Active Rising Edge)
Truth Table
Inputs
CP
X
X
X
S
D
L
L
H
H
C
D
H
L
L
J
K
X
X
l
O
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bs
o
Q
H
L
H
L
Q
L
H
H
X
X
X
l
l
h
h
X
l
H
N
N
N
N
H
H
H
H
H
H
h
H
H
h
L
X
X
H (h) = HIGH Voltage Level
L (l) = LOW Voltage Level
N
= LOW-to-HIGH Transition
X = Immaterial
Q
0
(Q
0
) = Before LOW-to-HIGH Transition of Clock
Lower case letters indicate the state of the referenced output one setup time prior to the LOW-to-HIGH clock transition.
le
Outputs
H
Toggle
Q
0
H
Q
0
Q
0
L
Q
0
PrintDate=1997/08/28 PrintTime=11:45:23 10182 ds009471 Rev. No. 1
cmserv
Proof
2
Logic Diagram
(One Half Shown)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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PrintDate=1997/08/28 PrintTime=11:45:24 10182 ds009471 Rev. No. 1
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Proof
3
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DS009471-5
Absolute Maximum Ratings
(Note 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
Plastic
V
CC
Pin Potential to
Ground Pin
Input Voltage (Note 4)
Input Current (Note 4)
Voltage Applied to Output
in HIGH State (with V
CC
= 0V)
Standard Output
TRI-STATE
®
Output
−65˚C
−55˚C
−55˚C
−55˚C
to
to
to
to
+150˚C
+125˚C
+175˚C
+150˚C
Current Applied to Output
in LOW State (Max)
ESD Last Passing Voltage (Min)
twice the rated I
OL
(mA)
4000V
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Commercial
Supply Voltage
Military
Commercial
−55˚C to +125˚C
0˚C to +70˚C
+4.5V to +5.5V
+4.5V to +5.5V
−0.5V to +7.0V
−0.5V to +7.0V
−30 mA to +5.0 mA
−0.5V to V
CC
−0.5V to +5.5V
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
Parameter
Min
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
V
OL
Output LOW
Input HIGH
2.0
le
0.8
V
−1.2
V
Min
2.5
2.5
2.7
V
Min
0.5
0.5
µA
µA
µA
V
µA
mA
mA
mA
mA
Max
Max
Max
0.0
0.0
Max
Max
Max
Max
V
Min
20.0
5.0
100
7.0
250
50
4.75
3.75
−0.6
−1.8
−60
11.7
−150
17.0
74F
T
A
= +25˚C
V
CC
= +5.0V
C
L
= 50 pF
Min
Typ
125
Max
Min
70
Max
Min
90
54F
T
A
, V
CC
= Mil
C
L
= 50 pF
100
4
54F 10% V
CC
74F 10% V
CC
74F 5% V
CC
54F 10% V
CC
54F
bs
o
Voltage
Current
74F 10% V
CC
74F
I
IH
I
BVI
Input HIGH Current
Output HIGH
54F
54F
Breakdown Test
74F
I
CEX
V
ID
Leakage Current
Input Leakage
74F
74F
Test
I
OD
I
IL
Output Leakage
74F
Circuit Current
Input LOW Current
O
I
OS
I
CC
Output Short-Circuit Current
Power Supply Current
AC Electrical Characteristics
DSXXX
See Section 0 for Waveforms and Load Configurations
74F
T
A
, V
CC
= Com
C
L
= 50 pF
Max
MHz
kk-kk
Fig.
Units
No.
Symbol
Parameter
f
max
Maximum Clock
Frequency
te
54F/74F
Typ
Units
V
V
CC
Max
I
OH
= −1 mA
I
OH
= −1 mA
I
OH
= −1 mA
I
OL
= 20 mA
I
OL
= 20 mA
V
IN
= 2.7V
V
IN
= 7.0V
V
OUT
= V
CC
I
ID
= 1.9 µA
CP = 0V
Note 3:
Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under these
conditions is not implied.
Note 4:
Either voltage limit or current limit is sufficient to protect inputs.
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18 mA
All Other Pins Grounded
V
IOD
= 150 mV
All Other Pins Grounded
V
IN
= 0.5V (J
n
, K
n
)
V
IN
= 0.5V (C
Dn
, S
Dn
)
V
OUT
= 0V
DSXXX
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PrintDate=1997/08/28 PrintTime=11:45:27 10182 ds009471 Rev. No. 1
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Proof
4
AC Electrical Characteristics
(Continued)
DSXXX
See Section 0 for Waveforms and Load Configurations
74F
T
A
= +25˚C
V
CC
= +5.0V
C
L
= 50 pF
Min
t
PLH
t
PHL
t
PLH
t
PHL
Propagation Delay
CP
n
to Q
n
or Q
n
Propagation Delay
C
Dn
or S
Dn
to
Q
n
or Q
n
3.8
4.4
3.2
3.5
Typ
5.3
6.2
5.2
7.0
Max
7.0
8.0
7.0
9.0
Min
3.8
4.4
3.2
3.5
Max
9.0
10.5
9.0
11.5
Min
3.8
4.4
3.2
3.5
Max
8.0
9.2
8.0
10.5
ns
kk-kk
ns
kk-kk
54F
T
A
, V
CC
= Mil
C
L
= 50 pF
74F
T
A
, V
CC
= Com
C
L
= 50 pF
Fig.
Units
No.
Symbol
Parameter
DSXXX
DSXXX
AC Operating Requirements
See Section 0 for Waveforms
Symbol
Parameter
74F
= +25˚C
T
A
V
CC
= +5.0V
Min
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
w
(H)
t
w
(L)
t
w
(L)
t
rec
Setup Time, HIGH or LOW
J
n
or K
n
to CP
n
Hold Time, HIGH or LOW
J
n
or K
n
to CP
n
CP
n
Pulse Width
HIGH or LOW
C
Dn
or S
Dn
Pulse Width,
LOW
Recovery Time
3.0
3.0
1.0
1.0
4.0
4.0
Max
te
54F
T
A
, V
CC
= Mil
74F
T
A
, V
CC
= Com
Min
3.0
3.0
1.0
Max
Units
Fig.
No.
Min
3.0
4.0
1.0
Max
ns
kk-kk
1.0
1.0
4.0
4.0
ns
ns
ns
kk-kk
kk-kk
kk-kk
5.0
5.0
4.0
4.0
2.0
2.0
DS009471-7
DSXXX
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DSXXX
DSXXX
5.0
bs
o
2.0
C
Dn
or S
Dn
to CP
DSXXX
DSXXX
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are de-
fined as follows:
Book
Extract
End
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PrintDate=1997/08/28 PrintTime=11:45:30 10182 ds009471 Rev. No. 1
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