ICS307-01/02
S
ERIALLY
P
ROGRAMMABLE
C
LOCK
S
OURCE
Description
The ICS307-01 and ICS307-02 are versatile serially
programmable clock sources which take up very little
board space. They can generate any frequency from 6
to 200 MHz and have a second configurable output.
The outputs can be reprogrammed on the fly and will
lock to a new frequency in 10 ms or less. Smooth
transitions (in which the clock duty cycle remains near
50%) are guaranteed if the output divider is not
changed.
The devices includes a PDTS pin which tri-states the
output clocks and powers down the entire chip.
The ICS307-02 features a default clock output at
start-up and is recommended for all new designs.
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined nor guaranteed.
For applications which require defined input to output
skew, use the ICS527-01.
Features
•
Packaged in 16-pin (150 mil wide) SOIC
•
ICS307M-02 and -02I available in Pb (lead) free
package
•
Highly accurate frequency generation
•
Serially programmable: user determines the output
frequency via a 3 wire interface
•
•
•
•
•
•
•
•
Eliminates need for custom quartz
Input crystal frequency of 5 - 27 MHz
Output clock frequencies up to 200 MHz
Power down tri-state mode
Very low jitter
Operating voltage of 3.3 V or 5 V
25 mA drive capability at TTL levels
Industrial temperature version available
Block Diagram
VDD
TTL
SCLK
DATA
STROBE
X1/ICLK
Crystal or
clock input
Crystal
Oscillator
X2
Shift
Register
9
2
3
2
7
R6:R7
Reference
Divider
V8:V0
C1:C0
S2:S0
F1:F0
VCO
Divider
CLK1
Phase Comparator,
Charge Pump, and
Loop Filter
VCO
Output
Divider
Function
Select
3
S2:S0
GND
3
F1:F0
PDTS
CLK2
Optional crystal capacitors
MDS 307-01/02 G
I n t e gra te d C i r c u i t S y s t e m s
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5 25 Race Stre et, San Jo se, CA 9 5126
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Revision 031606
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ICS307-01/02
S
ERIALLY
P
ROGRAMMABLE
C
LOCK
S
OURCE
Pin Assignment
X1/ICLK
NC
VDD
NC
GND
CLK2
NC
SCLK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X2
NC
NC
PDTS
DATA
CLK1
NC
STRO BE
16 pin (150 m il) SO IC
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
Name
X1/ICLK
NC
VDD
NC
GND
CLK2
NC
SCLK
STROBE
NC
CLK1
DATA
PDTS
NC
NC
X2
Pin
Type
XI
-
Power
-
Power
Output
-
Input
Input
-
Output
Input
Input
-
-
XO
Pin Description
Crystal connection (REF frequency). Connect to a parallel resonant crystal or an
input clock.
No connect. Do not connect anything to this pin.
Connect to 3.3 V or 5 V.
No connect. Do not connect anything to this pin.
Connect to ground.
Output clock 2, determined by F0 - F1. Can be reference, REF/2, CLK1/2 , or off.
No connect. Do not connect anything to this pin.
Serial clock. See timing diagram.
Strobe to load data. See timing diagram.
No connect. Do not connect anything to this pin.
Output clock 1, determined by R0 - R6, V0 - V8, S0 - S2, and input frequency.
Data input. Serial input for three words which set the output clock(s).
Powers down entire chip, tri states CLK1 and CLK2 outputs when low. Internal
pull-up.
No connect. Do not connect anything to this pin.
No connect. Do not connect anything to this pin.
Input crystal connection. Connect to a crystal or leave unconnected for clock
input.
MDS 307-01/02 G
In te grated Circuit Systems
●
2
525 Ra ce Street, San Jose, CA 9512 6
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Revision 031606
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ICS307-01/02
S
ERIALLY
P
ROGRAMMABLE
C
LOCK
S
OURCE
Determining the Output Frequency
On power-up, the ICS307-01 on-chip registers can
have random values so almost any frequency may be
output from the part. CLK1 will always have some clock
signal present, but CLK2 could possibly be OFF (low).
The ICS307-02 on-chip registers are initially configured
to provide a x1 output clock on both the CLK1 and
CLK2 outputs. The output frequency will be the same
as the input clock or crystal. This is useful if the ICS307
will provide the initial system clock at power-up. Since
this feature is an advantage in most systems, the
ICS307-02 is recommended for new designs.
With programming, the user has full control in changing
the desired output frequency to any value over the
range shown in Table 1 on page 4. The output of the
ICS307 can be determined by the following equation:
VDW + 8
-
CLK1Frequency
=
InputFrequency
⋅
2
⋅
------------------------------------------
(
RDW
+
2
) ⋅
OD
To determine the best combination of VCO, reference,
and output dividers, see the online calculator at
http://www.icst.com/products/ics307inputForm.html
or
contact ICS by sending an e-mail to ics-mk@icst.com
with the desired input crystal or clock and the desired
output frequency.
Where:
VCO Divider Word (VDW) = 4 to 511 (0, 1, 2, 3
are not permitted)
Reference Divider Word (RDW) = 1 to 127 (0 is
not permitted)
Output Divider = values on page 4
The following operating ranges should be observed.
For the commercial temperature range:
VDW + 8
55MHz
<
InputFrequency
⋅
2
⋅
------------------------ < 400MHz
RDW + 2
InputFrequency
-
200kHz
<
---------------------------------------------
RDW
+
2
And for the industrial temperature range:
VDW + 8
60MHz
<
InputFrequency
⋅
2
⋅
------------------------ < 360MHz
RDW + 2
Input Frequency
200kHz < ------------------------------------------
-
RDW + 2
MDS 307-01/02 G
In te grated Circuit Systems
●
3
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 031606
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w w w. i c s t . c o m
ICS307-01/02
S
ERIALLY
P
ROGRAMMABLE
C
LOCK
S
OURCE
Setting the Device Characteristics
The tables below show the settings which can be configured, as well as the VCO and Reference dividers.
Table 1. Output Divide and Maximum Output Frequency
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
CLK1 Output
Divide
10
2
8
4
5
7
3
6
Max. Frequency
5 V or 3.3 V (MHz)
40
200
50
100
80
55
135
67
Max. Frequency
Industrial Temp. Version
36
180
45
90
72
50
120
60
Table 2. CLK2 Output
F1
0
0
1
1
F0
0
1
0
1
CLK2
REF
F
REF
/2
OFF (Low)
F
CLK1
/2
Table 3. Output Duty Cycle Configuration
TTL
0
1
Duty Cycle Measured At
1.4 V
VDD/2
Recommended VDD
5V
3.3 V
Note: The TTL bit optimizes the duty cycle at different VDD. When VDD is 5 V, set to 0 for a near-50% duty
cycle with TTL levels. When VDD is 3.3 V, set this bit to 1 so the 50% duty cycle is achieved at VDD/2.
Table 4. Crystal Load Capacitance
C1
0
0
1
1
C0
0
1
0
1
VDD = 5V
22.3 - 0.083 f
23.1 - 0.093 f
23.7 - 0.106 f
24.4 - 0.120 f
VDD = 3.3V
22.1 - 0.094 f
22.9 - 0.108 f
23.5 - 0.120 f
24.2 - 0.135 f
Note: f is the crystal frequency in MHz between 10 and 27 MHz. Effective load capacitance will be higher
for crystal frequencies lower than 10 MHz. If a clock input is used, set C1 = 0 and C0 = 0.
MDS 307-01/02 G
In te grated Circuit Systems
●
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525 Ra ce Street, San Jose, CA 9512 6
●
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ICS307-01/02
S
ERIALLY
P
ROGRAMMABLE
C
LOCK
S
OURCE
Bypass Mode
If R6:0 is programmed to 0000000, the PLL is powered down and bypassed; the reference frequency will
come from both CLK1 and CLK2. It is possible to generate glitches going into and out of this mode.
Configuring the ICS307
The ICS307 can be programmed to set the output functions and frequencies. The three data bytes are
written in DATA pin in this order:
C1
MSB
C0
TTL
F1
F0
S2
S1
S0
LSB
V8
MSB
V7
V6
V5
V4
V3
V2
V1
LSB
V0
MSB
R6
R5
R4
R3
R2
R1
R0
LSB
C1 is loaded into the port first and R0 last.
R6:R0 Reference Divder Word (RDW)
V8:V0 VCO Divider Word (VDW)
S2:S0 Output Divider Select (OD)
F1:F0 Function of CLK2 Output
TTL
Duty Cycle Settings
C1:C0 Internal Load Capacitance for Crystal
The ICS307 can be reprogrammed at any time during operation. If R6:0, V8:0, TTL, or C1:0 are changed, the
frequency will transition smoothly to the new value over about 1 ms, without glitches or short cycles. If S2:0 is
changed, it is possible to generate glitches on CLK1 and also on CLK2 for F1:0 = 1 1.
Changing F1:0 will generate glitches on CLK2.
Power up default values for ICS307-02
0
0
1
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
The input frequency will come from both outputs.
A warning about using the default configuration with input frequencies lower than 13.75 MHz
The VCO will run only as low as its minimum frequency, which is guaranteed to be no more than 55 MHz.
So, in the powerup default condition, the PLL is guaranteed to lock to the input frequency down to 55/4 =
13.75 MHz. However, the part will typically run much slower. The typical minimum VCO frequency is about
30 - 40 MHz, depending on voltage, temperature, and lot variation; so in the powerup default setting, the
CLK2 output will be a minimum of 7.5 - 10 MHz even if the input frequency is lower than that. The output is
not locked to the reference input and so the frequency is not very stable and the phase noise is higher. In
this condition, the CLK2 output will accurately provide the reference frequency down to 0 Hz because this
signal path bypasses the PLL.
Power-down Mode
When the PDTS pin is pulled low, the chip will enter the power-down mode, where the output clocks are
tri-stated and the rest of the chip is powered down. The chip can be programmed during power-down
mode, however, if the chip is programmed during operation and enters power-down mode, the registers will
return to their settings and not reset when exiting power-down mode (PDTS pin is pulled high).
MDS 307-01/02 G
In te grated Circuit Systems
●
5
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 031606
tel (4 08) 297 -1 201
●
w w w. i c s t . c o m
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