EEWORLDEEWORLDEEWORLD

Part Number

Search

8N4Q001KG-0023CDI8

Description
IC osc clock QD freq 10clcc
Categorysemiconductor    Analog mixed-signal IC   
File Size163KB,20 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Download Datasheet View All

8N4Q001KG-0023CDI8 Online Shopping

Suppliers Part Number Price MOQ In stock  
8N4Q001KG-0023CDI8 - - View Buy Now

8N4Q001KG-0023CDI8 Overview

IC osc clock QD freq 10clcc

Quad-Frequency Programmable XO IDT8N4Q001 REV G
DATA SHEET
General Description
The IDT8N4Q001 is a Quad-Frequency Programmable Clock
Oscillator with very flexible frequency programming capabilities. The
device uses IDT’s fourth generation FemtoClock® NG technology for
an optimum high clock frequency and low phase noise performance.
The device accepts 2.5V or 3.3V supply and is packaged in a small,
lead-free (RoHS 6) 10-lead ceramic 5mm x 7mm x 1.55mm package.
Besides the four default power-up frequencies set by the FSEL0 and
FSEL1 pins, the IDT8N4Q001 can be programmed via the I
2
C
interface to output clock frequencies between 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz to a very high degree of
precision with a frequency step size of 435.9Hz ÷
N
(N is the PLL
output divider). Since the FSEL0 and FSEL1 pins are mapped to four
independent PLL divider registers (P, MINT, MFRAC and N),
reprogramming those registers to other frequencies under control of
FSEL0 and FSEL1 is supported. The extended temperature range
supports wireless infrastructure, telecommunication and networking
end equipment requirements.
Features
Fourth generation FemtoClock® NG technology
Programmable clock output frequency from 15.476MHz to
866.67MHz and from 975MHz to 1,300MHz
Four power-up default frequencies (see part number order
codes), re-programmable by I
2
C
I
2
C programming interface for the output clock frequency and
internal PLL control registers
Frequency programming resolution is 435.9Hz ÷N
One 2.5V, 3.3V LVDS clock output
Two control inputs for the power-up default frequency
LVCMOS/LVTTL compatible control inputs
RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.253ps
(typical), integer PLL feedback configuration
RMS phase jitter @ 156.25MHz (1kHz - 40MHz): 0.263ps
(typical), integer PLL feedback configuration
Full 2.5V or 3.3V supply modes
-40°C to 85°C ambient operating temperature
Available in Lead-free (RoHS 6) package
Block Diagram
OSC
f
XTAL
÷MINT,
MFRAC
2
25
FSEL1
FSEL0
SCLK
SDATA
OE
Pulldown
Pulldown
Pullup
Pullup
Pullup
Pin Assignment
÷P
PFD
&
LPF
FemtoClock® NG
VCO
1950-2600MHz
÷N
Q
nQ
DNU 1
OE 2
GND 3
FSEL0 4
FSEL1 5
10 SCLK
9 SDATA
8 V
DD
7 nQ
6 Q
7
Configuration Register (ROM)
(Frequency, APR, Polarity)
I
2
C Control
IDT8N4Q001
10-lead ceramic 5mm x 7mm x 1.55mm
package body
CD Package
Top View
IDT8N4Q001GCD
REVISION A
MARCH 6, 2012
1
©2012 Integrated Device Technology, Inc.
Please help me, there seems to be something wrong with the development board
Yesterday the development board was working fine. Today I changed a program and it didn't work when I downloaded it again. I changed to a program that I used to use. The program can be downloaded, but...
zhenpeng25 FPGA/CPLD
busybox 1.1.0
An error occurred when cross-compiling busybox 1.1.0 with 4.4.3 /home/bsec/busybox-1.1.0/libbb/procps.c:15:22: error: asm/page.h: No such find. After searching in many places , it was found that there...
bjwang Embedded System
Last year, I completed the drawing of the 4-layer PCB board for the router (or should I say the wiring was completed). I hope you can give me some advice.
[i=s]This post was last edited by chen468859 on 2017-1-24 16:38[/i] It was my first time drawing a 4-layer board. I was confused at first glance at so many schematic diagrams and components after they...
chen468859 PCB Design
Smart Home Assistant
What I envisioned cannot be completed independently by myself and requires teamwork. I can be responsible for the peripheral hardware design....
xu__changhua DSP and ARM Processors
Ask a question about VS2005
I downloaded the code from the Internet, and when I opened it, the following error message appeared: There was a failure while initializing the Microsoft Visual SourceSafe source control provider. You...
sinoxia Embedded System
51 serial port communication (dual 51 communication), question about SM2 bit
The experiment of two-machine communication (serial port working in mode 1) was not smooth. I tried to transfer three data directly according to the routine in the textbook, but it was unsuccessful. (...
辛昕 51mcu

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1516  2065  2545  74  523  31  42  52  2  11 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号