IDTCV183-2B
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PROGRAMMABLE FLEXPC CLOCK
IDTCV183-2B
FEATURES:
•
•
•
•
•
•
•
Compliant with Intel CK505 Gen II spec
One high precision PLL for CPU, SSC and N programming
One high precision PLL for SRC, SSC and N programming
One high precision PLL for SATA/PCI, and SSC
One high precision PLL for 96MHz/48MHz
Push-pull IOs for differential outputs
Support spread spectrum modulation, –0.5 down spread and
others
• Support SMBus block read/write, byte read/write
• Available in TSSOP package
KEY FEATURES
• Internal serial resistor can be enabled by SMBus control
register B19b7 to save the board space and material cost
• Direct CPU and SRC clock frequency programming—write the
Hex number into Byte [16:18], 1 MHz stepping.
• Linear and smooth transition for the CPU and SRC frequency
programming.
• Four Power On hardware modes – see page 6, CFG configu-
ration table 2.
• CV183-2 – When CFG[1:0] = 11, SATA clock power on default is
from SRC PLL.
OUTPUTS:
•
•
•
•
•
•
•
•
2*0.7V differential CPU CLK pair
10*0.7V differential SRC CLK pair
One CPU_ITP/SRC differential clock pair
One SRC0/DOT96 differential clock pair
6*PCI, 33.3MHz
1*48MHz
1*REF
1*SATA
KEY SPECIFICATIONS:
•
•
•
•
CPU/SRC CLK cycle to cycle jitter < 85ps
PCI CLK cycle to cycle jitter < 500ps
All SRC, SRC[0:11] phase noise < 3.10s RMS, PCIE Gen II
SRC3, 4, 6, 7, designated PCIE Gen II outputs, nominal
interpair skew = 0 ps
FUNCTIONAL BLOCK DIAGRAM
REF
XTAL_IN
PLL1
SSC
N Programmable
XTAL
Osc Amp
CPU[1:0]
CPU
Output Buffer
Stop Logic
XTAL_OUT
CPU_ITP/SRC8
SDATA
SCLK
SM Bus
Controller
PLL3
SSC
PCI/SATA
SRC CLK
Output Buffer
Stop Logic
PLL4
SSC
N Programmable
SRC1/SE
PCI[4:0], PCIF5
SATA/SRC2
CKPWRGD/PD#
CPU_STOP#
PCI_STOP#
SRC5_EN, TME
ITP_EN
CR_[H:A]#
FSC,B,A
Control
Logic
SRC CLK
Output Buffer
Stop Logic
SRC[7:3], [11:9]
48MHz
Fixed PLL
PLL2
48MHz/96MHz
Output BUffer
DOT96/SRC0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
© 2011 Integrated Device Technology, Inc.
MAY, 2011
DSC 7161
IDTCV183-2B
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
PCI0/CR#_A
V
DD
_PCI
PCI1/CR#_B
PCI2/TME
PCI3/CFGP
PCI4/SRC5_EN
PCIF5/ITP_EN
V
SS
_PCI
V
DD
_48MHz
USB_48/FSA
V
SS
_48MHz
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
6
4
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
3
SCL
SDA
REF/FSC/TEST_SEL
V
DD
_REF
XTAL_IN
XTAL_OUT
V
SS
_REF
FSB/TEST_MODE
CKPWRGD/PD#
V
DD
_CPU
CPUT0
CPUC0
V
SS
_CPU
CPUT1
V
DD
_IO
DOT96T/SRCT0
DOT96C/SRCC0
V
SS
_IO
CPUC1
V
DD
_CPU_IO
IO_V
OUT
V
DD
_PLL3
SRCT1/SE1
SRCC1/SE2
V
SS
_PLL3
V
DD
_PLL3_IO
SATAT/SRCT2
SATAC/SRCC2
V
SS
_SRC
SRCT3/CR#_C
SRCC3/CR#_D
V
DD
_SRC_IO
SRCT4
SRCC4
V
SS
_SRC
SRCT9
SRCC9
SRCC11/CR#_G
SRCT8/CPU_ITPT
SRCC8/CPU_ITPC
V
DD
_SRC_IO
SRCT7/CR#_F
SRCC7/CR#_E
V
SS
_SRC
SRCT6
SRCC6
V
DD
_SRC
PCI_STOP#/SRCT5
CPU_STOP#/SRCC5
V
DD
_SRC_IO
SRCC10
SRCT10
SRCT11/CR#_H
TSSOP
TOP VIEW
2
IDTCV183-2B
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Name
PCI0/CR#_A
V
DD
_PCI
PCI1/CR#_B
PCI2/TME
PCI3/CFGP
PCI4/SRC5_EN
PCIF5/ITP_EN
V
SS
_PCI
V
DD
_48
USB 48/FS_A
V
SS
_48
V
DD
_IO
SRCT0/DOT96T
SRCC0/DOT96C
V
SS
_IO
V
DD
_PLL3
SRCT1/SE1
SRCC1/SE2
V
SS
_PLL3
V
DD
_PLL3_IO
SATAT/SRCT2
SATAC/SRCC2
V
SS
_SRC
SRCT3/CR#_C
SRCC3/CR#_D
V
DD
_SRC_IO
SRCT4
SRCC4
V
SS
_SRC
SRCT9
SRCC9
SRCC11/CR#_G
SRCT11/CR#_H
SRCT10
SRCC10
V
DD
_SRC_IO
CPU_Stop#/SRCC5
PCI_Stop#/SRCT5
V
DD
_SRC
SRCC6
SRCT6
V
SS
_SRC
Type
I/O
PWR
I/O
I/O
OUT
I/O
I/O
GND
PWR
I/O
GND
PWR
OUT
OUT
GND
PWR
OUT
OUT
GND
PWR
OUT
OUT
GND
I/O
I/O
PWR
OUT
OUT
GND
OUT
OUT
I/O
I/O
OUT
OUT
PWR
I/O
I/O
PWR
OUT
OUT
GND
Description
33.33MHz. SRC0, 2 Differential clock output enable, control SRC0 and SRC2, 0 = enable. Mode is
selected by SMBus control register. Default is PCI clock mode.
3.3V
33.33MHz. SRC1, 4 Differential clock output enable, control SRC1 and SRC4, 0 = enable. Mode is
selected by SMBus control register. Default is PCI clock mode.
33.33MHz. Trust mode enable. HIGH = overclocking disabled. Power-on latch.
33.33MHz. Clock configuration bit, combined with pin 4 (see CFG Table), power on latch
33.33MHz. Pin 37, 38 mode selection. Power on latch, HIGH = SRC5, LOW = CPU and PCI Stop#.
33.33MHz. Pin 46, 47 mode selection. Power on latch, HIGH = CPU_ITP, LOW = SRC8.
GND
3.3V
48MHz, frequency select, power on latch
GND
0.8V
Differential output clock. SRC or DOT96. Mode selected by SMBus control register, default is SRC0.
Differential output clock. SRC or DOT96. Mode selected by SMBus control register, default is SRC0.
GND
3.3V
Differential or single end clock output. Mode selected by SMBus control register. Default is SRC1.
Differential or single end clock output. Mode selected by SMBus control register. Default is SRC1.
GND
0.8V
Differential output clock
Differential output clock
GND
SRC clock. SRC differential clock output enable, control SRC0 and SRC2, 0 = enable. Mode selected
by SMBus control register. Default is SRC3.
SRC clock. SRC differential clock output enable, control SRC1 and SRC4, 0 = enable. Mode selected
by SMBus control register. Default is SRC3.
0.8V
Differential output clock
Differential output clock
GND
Differential output clock
Differential output clock
SRC clock. SRC differential clock output enable, control SRC9, 0 = enable. Mode selected by SMBus
control register. Default is SRC11.
SRC clock. SRC differential clock output enable, control SRC10, 0 = enable. Mode selected by SMBus
control register. Default is SRC11.
Differential output clock
Differential output clock
0.8V
CPU stop, LOW = stop. SRC clock. Mode selected by pin6, SRC5_EN.
PCI stop, LOW = stop. SRC clock. Mode selected by pin6, SRC5_EN.
3.3V
Differential output clock
Differential output clock
GND
3
IDTCV183-2B
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION, CONTINUED
Pin #
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Name
SRCC7/CR#_E
SRCT7/CR#_F
V
DD
_SRC_IO
SRCC8/CPU_ ITPC
SRCT8/CPU_ ITPT
IO_V
OUT
V
DD
_CPU_IO
CPUC1
CPUT1
V
SS
_CPU
CPUC0
CPUT0
V
DD
_CPU
CKPWRGD/PD#
FS_B/TestMode
V
SS
_REF
XTAL_OUT
XTAL_IN
V
DD
_REF
REF/FS_C/TestSel
SDA
SCL
Type
I/O
I/O
PWR
OUT
OUT
OUT
PWR
OUT
OUT
GND
OUT
OUT
PWR
IN
IN
GND
OUT
IN
PWR
I/O
I/O
IN
Description
SRC clock. SRC differential clock output enable, control SRC6, 0 = enable. Mode selected by SMBus
control register. Default is SRC7.
SRC clock. SRC differential clock output enable, control SRC8, 0 = enable. Mode selected by SMBus
control register. Default is SRC7.
0.8V
SRC clock. CPU clock. Mode selected by pin7.
SRC clock. CPU clock. Mode selected by pin7.
V_IO adjustment
0.8V
Differential output clock
Differential output clock
GND
Differential output clock
Differential output clock
3.3V
CKPWRGD power good, active LOW, used to latch FSA,B,C, ITP_EN, TME, and SRC5_EN , active HIGH.
After, becomes power down, LOW active.
Frequency Select at CKPWRGD assertion. Test Mode selection, see TEST_MODE selection table.q
GND
XTAL out
XTAL in
3.3V
14.318MHz. Frequency Select at CKPWRGD assertion. Selects test mode if pulled above 2V at CKPWRGD
assertion.
SMBus clock
SMBus data
TEST MODE SELECTION
(1)
Test_Mode
1
0
CPU
REF/N
Hi-Z
SRC
REF/N
Hi-Z
If TEST_SEL sampled above 2V at CKPWRGD active LOW
PCI/F
REF/N
Hi-Z
REF
REF
Hi-Z
DOT_96/DOT_SSC
REF/N
Hi-Z
USB
REF/N
Hi-Z
NOTE:
1. Once test clock operation has been invoked, TEST_MODE pin will select between the Hi-Z and REF/N, with V
IH
_FS and V
IL
_FS thresholds.
FREQUENCY SELECTION
FSC, B, A
101
001
011
010
000
100
110
111
CPU
100
133
166
200
266
333
400
Reserve
SRC[7:0]
100
100
100
100
100
100
100
100
PCI
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
4
USB
48
48
48
48
48
48
48
48
DOT
96
96
96
96
96
96
96
96
REF
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
IDTCV183-2B
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
DDA
V
DD
T
STG
T
AMBIENT
T
CASE
ESD Prot
Description
3.3V Core Supply Voltage
3.3V Logic Input Supply Voltage GND - 0.5
Storage Temperature
Ambient Operating Temperature
Case Temperature
Input ESD Protection
Human Body Model
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
INDEX BLOCK READ PROTOCOL
Unit
V
V
°C
°C
°C
V
Bit
1
2-9
10
11-18
19
20
21-28
29
30-37
38
39-46
47
48-55
# of bits
1
8
1
8
1
1
8
1
8
1
8
1
8
From
Master
Master
Slave
Master
Slave
Master
Master
Slave
Slave
Master
Slave
Master
Slave
Description
Min
Max
4.6
4.6
+150
+70
+115
Master can stop reading any time by issuing the stop bit without waiting
until Nth byte (byte count bit 30-37).
Start
D2h
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Repeated Start
D3h
Ack (Acknowledge)
Byte count, N (block read back of N
bytes)
Ack (Acknowledge)
first data byte (Offset data byte)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
:
Ack (Acknowledge)
Nth data byte
Not acknowledge
Stop
–65
0
2000
SM PROTOCOL
INDEX BLOCK WRITE PROTOCOL
Bit
1
2-9
10
11-18
19
20-27
28
29-36
37
38-45
46
# of bits
1
8
1
8
1
8
1
8
1
8
1
From
Master
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Description
Start
D2h
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Byte count, N (0 is not valid)
Ack (Acknowledge)
first data byte (Offset data byte)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
:
Nth data byte
Acknowledge
Stop
Master
Slave
Master
5
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