Datasheet
RX210 Group
Renesas MCUs
R01DS0041EJ0120
Rev.1.20
Nov 28, 2012
50-MHz 32-bit RX MCUs, 78 DMIPS, up to 512-KB flash memory,
12-bit A/D, 10-bit D/A, ELC, MPC, RTC, up to 9 comms channels;
incorporating functions for IEC60730 compliance
Features
■
32-bit RX CPU core
Max. operating frequency: 50 MHz
Capable of 78 DMIPS in operation at 50 MHz
Accumulator handles 64-bit results (for a single
instruction) from 32- × 32-bit operations
Multiplication and division unit handles 32- × 32-bit
operations (multiplication instructions take one CPU
clock cycle)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions, ultra-compact code
On-chip debugging circuit
■
Low power design and architecture
Operation from a single 1.62-V to 5.5-V supply
1.62-V operation available (at up to 20 MHz)
Deep software standby mode with RTC remaining usable
Four low power modes
■
On-chip flash memory for code, no wait states
50-MHz operation, 20-ns read cycle
No wait states for reading at full CPU speed
64-K to 512-Kbyte capacities
User code programmable via the SCI
Programmable at 1.62 V
For instructions and operands
■
On-chip data flash memory
8 Kbytes
(Number of times of reprogramming: 100,000)
Erasing and programming impose no load on the CPU.
■
On-chip SRAM, no wait states
12-K to 64-Kbyte size capacities
■
DMA
DMAC: Incorporates four channels
DTC: Four transfer modes
■
ELC
Module operation can be initiated by event signals
without going through interrupts.
Modules can operate while the CPU is sleeping.
■
Reset and supply management
Nine types of reset, including the power-on reset (POR)
Low voltage detection (LVD) with voltage settings
■
Clock functions
Frequency of external clock: Up to 20 MHz
Frequency of the oscillator for sub-clock generation:
32.768 kHz
PLL circuit input: 4 MHz to 12.5 MHz
On-chip low- and high-speed oscillators, dedicated on-
chip low-speed oscillator for the IWDT
Generation of a dedicated 32.768-kHz clock for the RTC
Clock frequency accuracy measurement circuit (CAC)
■
Real-time clock
Adjustment functions (30 seconds, leap year, and error)
Time capture function
Time capture on event-signal input through external pins
RTC capable of initiating return from deep software
standby mode
PLQP0100KB-A 14 × 14 mm, 0.5-mm pitch
PLQP0080KB-A 12 × 12 mm, 0.5-mm pitch
PLQP0064KB-A 10 × 10 mm, 0.5-mm pitch
PLQP0048KB-A 7 × 7 mm, 0.5-mm pitch
PLQP0080JA-A 14 × 14 mm, 0.65-mm pitch
PLQP0064GA-A 14 × 14 mm, 0.8-mm pitch
PTLG0100JA-A 7 × 7 mm, 0.65-mm pitch
PTLG0100KA-A 5.5 × 5.5 mm, 0.5-mm pitch
PTLG0064JA-A 6 × 6 mm, 0.65-mm pitch
■
Independent watchdog timer
125-kHz on-chip oscillator produces a dedicated clock
signal to drive IWDT operation.
■
Useful functions for IEC60730 compliance
Self-diagnostic and disconnection-detection assistance
functions for the A/D converter, clock frequency
accuracy measurement circuit, independent watchdog
timer, functions to assist in RAM testing, etc.
■
Up to nine communications channels
SCI with many useful functions (up to seven channels)
Asynchronous mode, clock synchronous mode, smart
card interface
I
2
C bus interface: Transfer at up to 400 kbps, capable of
SMBus operation (one channel)
RSPI (one channel)
■
External address space
Four CS areas (4 × 16 Mbytes)
8- or 16-bit bus space is selectable per area
■
Up to 14 extended-function timers
16-bit MTU: input capture, output compare,
complementary PWM output, phase counting mode
(six channels)
8-bit TMR (four channels)
16-bit compare-match timers (four channels)
■
12-bit A/D converter
Capable of conversion within 1
μs
Sample-and-hold circuits (for three channels)
Three-channel synchronized sampling available
Self-diagnostic function and analog input disconnection
detection assistance function
■
10-bit D/A converter
■
Analog comparator
■
General I/O ports
5-V tolerant, open drain, input pull-up, switching of
driving ability
■
MPC
Multiple locations are selectable for I/O pins of
peripheral functions
■
Temperature sensor
■
Operating temp. range
40C
to +85C
40C
to +105C
R01DS0041EJ0120 Rev.1.20
Nov 28, 2012
Page 1 of 162
RX210 Group
1. Overview
1.Overview
1.1
Outline of Specifications
Table 1.1
lists the specifications in outline, and
Table 1.2
gives a comparison of the functions of products in different
packages.
Table 1.1
is for products with the greatest number of functions, so numbers of peripheral modules and channels will
differ in accord with the package. For details, see
Table 1.2, Comparison of Functions for Different Packages.
This product includes chip version A (part no.: R5F5210xAxxx), chip version B (part no.: R5F5210xBxxx), and chip
version C (part no: R5F5210xCxxx).
Table 1.1
Classification
CPU
Outline of Specifications (1 / 4)
Module/Function
CPU
Description
Maximum operating frequency: 50 MHz
32-bit RX CPU
Minimum instruction execution time: One instruction per state (cycle of the system clock)
Address space: 4-Gbyte linear
Register
General purpose: Sixteen 32-bit registers
Control: Eight 32-bit registers
Accumulator: One 64-bit register
Basic instructions: 73
DSP instructions: 9
Addressing modes: 10
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32
32
64 bits
On-chip divider: 32 / 32
32 bits
Barrel shifter: 32 bits
Memory
ROM
Capacity: 64 K/96 K/128 K/256 K/384 K/512 Kbytes
50 MHz, no-wait memory access
On-board programming: 3 types
Off-board programming (parallel programmer mode)
Capacity: 12 K/16 K/20 K/32 K/64 K Kbytes
50 MHz, no-wait memory access
Capacity: 8 Kbytes
Number of times for programming/erasing: 100,000
Single-chip mode, on-chip ROM enabled expansion mode, and on-chip ROM disabled expansion mode
(software switching)
Main clock oscillator, sub-clock oscillator, low-speed on-chip oscillator, high-speed on-chip oscillator,
PLL frequency synthesizer, and IWDT-dedicated on-chip oscillator
Oscillation stop detection
Measuring circuit for accuracy of clock frequency (clock-accuracy check: CAC)
Independent settings for the system clock (ICLK), peripheral module clock (PCLK), external bus clock
(BCLK), and flashIF clock (FCLK)
The CPU and system sections such as other bus masters run in synchronization with the system
clock (ICLK): 50 MHz (at max.)
Peripheral modules run in synchronization with the peripheral module clock (PCLK): 32 MHz (at
max.)
Devices connected to the external bus run in synchronization with the external bus clock (BCLK):
12.5 MHz (at max.)
The flash peripheral circuit runs in synchronization with the flash peripheral clock (FCLK): 32 MHz (at
max.)
RES# pin reset, power-on reset, voltage monitoring reset, watchdog timer reset, independent watchdog
timer reset, deep software standby reset, and software reset
RAM
E2 DataFlash
MCU operating mode
Clock
Clock generation circuit
Reset
Voltage detection
Voltage detection circuit
(LVDAa)
When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt
is generated.
Voltage detection circuit 0 is capable of selecting the detection voltage from 4 levels
Voltage detection circuit 1 is capable of selecting the detection voltage from 16 levels
Voltage detection circuit 2 is capable of selecting the detection voltage from 16 levels
R01DS0041EJ0120 Rev.1.20
Nov 28, 2012
Page 2 of 162
RX210 Group
Table 1.1
Classification
Low power
consumption
1. Overview
Outline of Specifications (2 / 4)
Module/Function
Low power consumption
facilities
Function for lower operating
power consumption
Description
Module stop function
Four low power consumption modes
Sleep mode, all-module clock stop mode, software standby mode, and deep software standby mode
Operating power control modes
[Chip versions A and C]
High-speed operating mode, middle-speed operating mode 1A, middle-speed operating mode 1B,
low-speed operating mode 1, low-speed operating mode 2
[Chip version B]
High-speed operating mode, middle-speed operating mode 1A, middle-speed operating mode 1B,
middle-speed operating mode 2A, middle-speed operating mode 2B, low-speed operating mode 1,
low-speed operating mode 2
Interrupt vectors: 117
External interrupts: 9 (NMI, IRQ0 to IRQ7 pins)
Non-maskable interrupts: 6 (the NMI pin, oscillation stop detection interrupt, voltage monitoring 1
interrupt, voltage monitoring 2 interrupt, WDT interrupt, and IWDT interrupt)
16 levels specifiable for the order of priority
The external address space can be divided into four areas (CS0 to CS3), each with independent
control of access settings.
Capacity of each area: 16 Mbytes (CS0 to CS3)
A chip-select signal (CS0# to CS3#) can be output for each area.
Each area is specifiable as an 8-bit or 16-bit bus space
The data arrangement in each area is selectable as little or big endian (only for data).
Bus format: Separate bus, multiplex bus
Wait control
Write buffer facility
4 channels
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Software trigger, external interrupts, and interrupt requests from peripheral
functions
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Interrupts
Chain transfer function
100-pin/80-pin/64-pin/48-pin
I/O pin: 84/64/48/34
Input: 1/1/1/1
Pull-up resistors: 84/64/48/34
Open-drain outputs: 54/44/35/26
5-V tolerance:4/4/2*
1
/2
Event signals of 59 types can be directly connected to the module
Operations of timer modules are selectable at event input
Capable of event link operation for ports B and E
Capable of selecting input/output function from multiple pins
Interrupt
Interrupt controller (ICUb)
External bus extension
DMA
DMA controller (DMACA)
Data transfer controller
(DTCa)
I/O ports
General I/O ports
Event link controller (ELC)
Multi-function pin controller (MPC)
R01DS0041EJ0120 Rev.1.20
Nov 28, 2012
Page 3 of 162
RX210 Group
Table 1.1
Classification
Timers
1. Overview
Outline of Specifications (3 / 4)
Module/Function
Multi-function timer pulse
unit 2 (MTU2a)
Description
(16 bits
6 channels)
1 unit
Time bases for the six 16-bit timer channels can be provided via up to 16 pulse-input/output lines and
three pulse-input lines
Select from among eight or seven counter-input clock signals for each channel (PCLK/1, PCLK/4,
PCLK/16, PCLK/64, PCLK/256, PCLK/1024, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than
channel 5, for which only four signals are available.
Input capture function
21 output compare/input capture registers
Pulse output mode
Complementary PWM output mode
Reset synchronous PWM mode
Phase-counting mode
Generation of triggers for A/D converter conversion
Controls the high-impedance state of the MTU’s waveform output pins
(8 bits
2 channels)
2 units
Select from among seven internal clock signals (PCLK1, PCLK/2, PCLK/8, PCLK/32, PCLK/64,
PCLK/1024, PCLK/8192) and one external clock signal
Capable of output of pulse trains with desired duty cycles or of PWM signals
The 2 channels of each unit can be cascaded to create a 16-bit timer
Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12
(16 bits
2 channels)
2 units
Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
14 bits
1 channel
Select from among 6 counter-input clock signals (PCLK/4, PCLK/64, PCLK/128, PCLK/512,
PCLK/2048, PCLK/8192)
14 bits
1 channel
Counter-input clock: IWDT-dedicated on-chip oscillator
Frequency divided by 1, 16, 32, 64, 128, or 256
Clock source: Sub-clock
Time/calendar
Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt
Time-capture facility for three values
Port output enable 2
(POE2a)
8-bit timer (TMR)
Compare match timer
(CMT)
Watchdog timer (WDTA)
Independent watchdog
timer (IWDTa)
Realtime clock (RTCb)
Communication
function
Serial communications
interfaces (SCIc, SCId)
7 channels (channel 0, 1, 5, 6, 8, 9: SCIc, channel 12: SCId)
Serial communications modes:
Asynchronous, clock synchronous, and smart-card interface
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Average transfer rate clock can be input from TMR timers (SCI5, SCI6, and SCI12)
Simple IIC
Simple SPI
Master/slave mode supported (SCId only)
Start frame and information frame are included (SCId only)
1 channel
Communications formats:
I
2
C bus format/SMBus format
Master/slave selectable
Supports the fast mode
1 channel
Transfer facility
Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select), and RSPI
clock (RSPCK) signals enables serial transfer through SPI operation (four lines) or clock-
synchronous operation (three lines)
Capable of handling serial transfer as a master or slave
Data formats
Choice of LSB-first or MSB-first transfer
The number of bits in each transfer can be changed to any number of bits from 8 to 16, 20, 24, or 32
bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or received in a single transfer operation (with each frame
having up to 32 bits)
Double buffers for both transmission and reception
I
2
C bus interface (RIIC)
Serial peripheral
interface (RSPI)
R01DS0041EJ0120 Rev.1.20
Nov 28, 2012
Page 4 of 162
RX210 Group
Table 1.1
Classification
1. Overview
Outline of Specifications (4 / 4)
Module/Function
Description
12 bits (16 channels
1 unit)
12-bit resolution
Minimum conversion time: 1.0
s
per channel (in operation with ADCLK at 50 MHz)
Operating modes
Scan mode (single scan mode, continuous scan mode, and group scan mode)
Sample-and-hold function
Self-diagnosis for the A/D converter
Assistance in detecting disconnected analog inputs
Double-trigger mode (duplication of A/D conversion data)
A/D conversion start conditions
A software trigger, a trigger from a timer (MTU), an external trigger signal, or ELC
12-bit A/D converter (S12ADb)
Temperature sensor (TEMPSa)
D/A converter (DA)
Outputs the voltage that changes depending on the temperature
PGA gain switchable: Four levels according to the voltage range
2 channels
10-bit resolution
Output voltage: 0 V to VREFH
CRC code generation for arbitrary amounts of data in 8-bit units
Select any of three generating polynomials:
X
8
+ X
2
+ X + 1, X
16
+ X
15
+ X
2
+ 1, or X
16
+ X
12
+ X
5
+ 1
Generation of CRC codes for use with LSB-first or MSB-first communications is selectable.
2 channels
Comparison of reference voltage and analog input voltage
2 channels
Comparison of reference voltage and analog input voltage
Comparison, addition, and subtraction of 16-bit data
VCC = 1.62 to 1.8 V: 20 MHz, VCC = 1.8 to 2.7 V: 32 MHz, VCC = 2.7 to 5.5 V: 50 MHz
14 mA @ 50MHz (typ.)
D version:
40
to +85C, G version:
40
to +105C
100-pin TFLGA (PTLG0100JA-A) 7 × 7 mm, 0.65-mm pitch
100-pin LQFP (PLQP0100KB-A) 14 × 14 mm, 0.5-mm pitch
80-pin LQFP (PLQP0080KB-A) 12 × 12 mm, 0.5-mm pitch
64-pin LQFP (PLQP0064KB-A) 10 × 10 mm, 0.5-mm pitch
100-pin TFLGA (PTLG0100JA-A) 7 × 7 mm, 0.65-mm pitch
100-pin TFLGA (PTLG0100KA-A) 5.5 × 5.5 mm, 0.5-mm pitch
64-pin TFLGA (PTLG0064JA-A) 6 × 6 mm, 0.65-mm pitch
100-pin LQFP (PLQP0100KB-A) 14 × 14 mm, 0.5-mm pitch
80-pin LQFP (PLQP0080KB-A) 12 × 12 mm, 0.5-mm pitch
80-pin LQFP (PLQP0080JA-A) 14 × 14 mm, 0.65-mm pitch
64-pin LQFP (PLQP0064KB-A) 10 × 10 mm, 0.5-mm pitch
64-pin LQFP (PLQP0064GA-A) 14 × 14 mm, 0.8-mm pitch
48-pin LQFP (PLQP0048KB-A) 7 × 7 mm, 0.5-mm pitch
100-pin TFLGA (PTLG0100JA-A) 7 × 7 mm, 0.65-mm pitch
100-pin LQFP (PLQP0100KB-A) 14 × 14 mm, 0.5-mm pitch
80-pin LQFP (PLQP0080KB-A) 12 × 12 mm, 0.5-mm pitch
80-pin LQFP (PLQP0080JA-A) 14 × 14 mm, 0.65-mm pitch
64-pin LQFP (PLQP0064KB-A) 10 × 10 mm, 0.5-mm pitch
64-pin LQFP (PLQP0064GA-A) 14 × 14 mm, 0.8-mm pitch
E1 emulator (FINE interface)
CRC calculator (CRC)
Comparator A (CMPA)
Comparator B (CMPB)
Data Operation Circuit (DOC)
Power supply voltage/Operating frequency
Supply current
Operating temperature
Package
Chip version A
Chip version B
Chip version C
On-chip debugging system
Note 1. In chip version A of the part numbers below, port P17 is not 5 V tolerant. Therefore there is only one port in these products.
R5F52108ADFM, R5F52107ADFM, R5F52106ADFM, and R5F52105ADFM
R01DS0041EJ0120 Rev.1.20
Nov 28, 2012
Page 5 of 162
DSP and ARM Processors
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