PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS889834
L
OW
S
KEW
, 2-
TO
-4
LVCMOS/LVTTL-
TO
-LVPECL/ECL C
LOCK
M
ULTIPLEXER
F
EATURES
•
Four differential LVPECL/ECL outputs
•
Two LVCMOS/LVTTL clock inputs
•
Output frequency: >1GHz (typical)
•
Output skew: TBD
•
Part-to-part skew: TBD
•
Additive jitter, RMS: <100fs (typical)
•
Propagation delay: 420ps (typical)
•
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.63V, V
EE
= 0V
•
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3.63V to -2.375V
•
-40°C to 85°C ambient operating temperature
•
Available in both standard and lead-free RoHS compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS889834 is a high speed 2-to-4 LVCMOS/
LVTTL-to-LVPECL/ECL Clock Multiplexer and is
HiPerClockS™
a member of the HiPerClockS™ family of high
performance clock solutions from ICS. The
ICS889834 is optimized for high speed and
very low output skew, making it suitable for use in demand-
ing applications such as SONET, 1 Gigabit and 10 Gigabit
Ethernet, and Fibre Channel. The device also has an output
enable pin which may be useful for system test and debug
purposes. The ICS889834 is packaged in a small 3mm x 3mm
16-pin VFQFN package which makes it ideal for use in space-
constrained applications.
IC
S
B
LOCK
D
IAGRAM
SEL
Q0
nQ0
IN1
1
MUX
IN2
0
Q2
D
EN
Q
nQ2
Q1
nQ1
P
IN
A
SSIGNMENT
nQ0
V
CC
Q1 1
nQ1 2
Q2 3
nQ2 4
16 15 14 13
12
11
10
9
5
Q3
V
EE
Q0
IN1
SEL
nc
IN2
6
nQ3
7
V
CC
8
EN
ICS889834
16-Lead VFQFN
3mm x 3mm x 0.95 package body
K Package
Top View
Q3
nQ3
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
889834AK
www.icst.com/products/hiperclocks.html
1
REV. A MARCH 20, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS889834
L
OW
S
KEW
, 2-
TO
-4
LVCMOS/LVTTL-
TO
-LVPECL/ECL C
LOCK
M
ULTIPLEXER
Type
Description
Differential output pair. LVPECL / ECL interface levels.
Differential output pair. LVPECL / ECL interface levels.
Differential output pair. LVPECL / ECL interface levels.
Positive supply pins.
Synchronizing clock enable. When LOW, Q outputs will go LOW and nQ
outputs will go HIGH on the next LOW transition at IN inputs. Input
threshold is V
CC
/2V. Includes a 37k
Ω
pull-up resistor. Default state is
HIGH when left floating. The internal latch is clocked on the falling edge
of the input signal (IN1, IN2). LVTTL / LVCMOS interface levels.
LVCMOS / LVTTL clock input.
No connect.
Pullup
Pullup
Select input pin. LVCMOS / LVTTL interface levels
LVCMOS / LVTTL clock input.
Negative supply pin.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 4
5, 6
7, 14
Name
Q1, nQ1
Q2, nQ2
Q3, nQ3
V
CC
Output
Output
Output
Power
8
EN
Input
Pullup
9
10
11
12
13
IN2
nc
SEL
IN1
V
EE
Input
Unused
Input
Input
Power
Pullup
1 5, 16
Q0, nQ0
Output
Differential output pair. LVPECL / ECL interface levels.
NOTE:
Pullup
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
R
PULLUP
Parameter
Input Pullup Resistor
Test Conditions
Minimum
Typical
37
Maximum
Units
kΩ
889834AK
www.icst.com/products/hiperclocks.html
2
REV. A MARCH 20, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS889834
L
OW
S
KEW
, 2-
TO
-4
LVCMOS/LVTTL-
TO
-LVPECL/ECL C
LOCK
M
ULTIPLEXER
Outputs
Q0:Q3
Disabled; LOW
nQ0:nQ3
Disabled; HIGH
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
EN
0
Selected Source
IN1, IN2
1
IN, IN2
Enabled
Enabled
After EN switches, the clock outputs are disabled or enabled following a falling input
clock edge as shown in
Figur
e
1.
Disabled
IN1,
IN2
EN
Enabled
nQx
Qx
F
IGURE
1. EN T
IMING
D
IAGRAM
T
ABLE
3B. T
RUTH
T
ABLE
Inputs
IN1
0
1
X
X
X
IN2
X
X
0
1
X
EN
1
1
1
1
0
SEL
1
1
0
0
X
0
1
0
1
0
(1)
Outputs
Q0:Q3
nQ0:nQ3
1
0
1
0
0
(1)
NOTE 1: On next negative transition of the input signal (IN).
889834AK
www.icst.com/products/hiperclocks.html
3
REV. A MARCH 20, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS889834
L
OW
S
KEW
, 2-
TO
-4
LVCMOS/LVTTL-
TO
-LVPECL/ECL C
LOCK
M
ULTIPLEXER
4.6V (LVPECL mode, V
EE
= 0)
NOTE:
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
-4.6V (ECL mode, V
CC
= 0)
to the device. These ratings are stress specifi-
-0.5V to V
CC
+ 0.5 V
cations only. Functional operation of product at
0.5V to V
EE
- 0.5V
these conditions or any conditions beyond those
50mA
100mA
±50mA
±100mA
-65°C to 150°C
51.5°C/W (0 lfpm)
listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Negative Supply Voltage, V
EE
Inputs, V
I
(LVPECL mode)
Inputs, V
I
(ECL mode)
Outputs, I
O
Continuous Current
Surge Current
Input Current, IN, nIN
V
T
Current, I
VT
Storage Temperature, T
STG
Package Thermal Impedance,
θ
JA
(Junction-to-Ambient)
Operating Temperature Range, TA -40°C to +85°C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.63V; V
EE
= 0V, T
A
= -40°C
TO
85°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
3.3
45
Maximum
3.63
Units
V
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= 2.5V±5%
OR
3.3V±10%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Test Conditions
Minimum
2
0
-125
Typical
Maximum
V
CC
+ 0.3
0.8
20
-300
Units
V
V
µA
µA
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= 2.5V±5%
OR
3.3V±10%, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
V
OUT
V
DIFF_OUT
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Voltage Swing
Differential Output Voltage Swing
Conditions
Minimum
V
CC
- 1.145
V
CC
- 1.945
550
1100
Typical
V
CC
- 1.020
V
CC
- 1.820
800
1600
Maximum
Units
V
V
mV
mV
Input and output parameters vary 1:1 with V
CC
.
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
889834AK
www.icst.com/products/hiperclocks.html
4
REV. A MARCH 20, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS889834
L
OW
S
KEW
, 2-
TO
-4
LVCMOS/LVTTL-
TO
-LVPECL/ECL C
LOCK
M
ULTIPLEXER
Condition
Minimum
Typical
>1.0
420
420
TBD
TBD
TBD
<100
20% to 80%
EN to IN1, IN2
EN to IN1, IN2
220
TBD
TBD
50
Maximum
Units
GH z
ps
ps
ps
ps
ps
fs
ps
ps
ps
%
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 2.5V±5%
OR
3.3V±10%, T
A
= -40°C
TO
85°C
Symbol
f
MAX
t
PLH
t
PHL
t
SW
t
sk(o)
t
sk(pp)
t
jit
t
R
/t
F
t
S
t
H
odc
Parameter
Output Frequency
Propagation Delay, Low-to-High;
NOTE 1
Propagation Delay, High-to-Low;
NOTE 1
Switchover Time
SEL to Q
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
Output Rise/Fall Time
Clock Enable Setup Time
Clock Enable Hold Time
Output Duty Cycle
All parameters characterized at
≤
1GHz unless otherwise noted.
NOTE 1: Measured from V
CC
/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
889834AK
www.icst.com/products/hiperclocks.html
5
REV. A MARCH 20, 2006
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