4:1 or 2:1 LVDS Clock Multiplexer with
Internal Input Termination
854S057
DATA SHEET
General Description
The 854S057 is a 4:1 or 2:1 LVDS Clock Multiplexer which can
operate up to 2GHz. The PCLK, nPCLK pairs can accept most
standard differential input levels. Internal termination is provided on
each differential input pair. The 854S057 operates using a 2.5V
supply voltage. The fully differential architecture and low propagation
delay make it ideal for use in high speed multiplexing applications.
The select pins have internal pulldown resistors. Leaving one input
unconnected (pulled to logic low by the internal resistor) will
transform the device into a 2:1 multiplexer. The SEL1 pin is the most
significant bit and the binary number applied to the select pins will
select the same numbered data input (i.e., 00 selects PCLK0,
nPCLK0).
Features
•
•
•
•
•
•
•
•
•
•
•
High speed differential multiplexer. The device can be configured
as either a 4:1 or 2:1 multiplexer
One LVDS output pair
Four selectable PCLK, nPCLK inputs with internal termination
PCLKx, nPCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, CML, SSTL
Maximum output frequency: 2GHz
Part-to-part skew: 200ps (maximum)
Propagation delay: 650ps (maximum)
Additive phase jitter, RMS: 0.047ps (typical)
Full 2.5V power supply
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
VT0
50
PCLK0
nPCLK0
VT1
50
PCLK1
nPCLK1
VT2
50
PCLK2
nPCLK2
VT3
50
PCLK3
nPCLK3
SEL1
Pulldown
SEL0
Pulldown
50
50
50
50
Pin Assignment
V
DD
PCLK0
VT0
nPCLK0
SEL1
SEL0
PCLK1
VT1
nPCLK1
GND
0 0
0 1
1 0
1 1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
PCLK3
VT3
nPCLK3
Q
nQ
PCLK2
VT2
nPCLK2
GND
854S057
Q
nQ
20-Lead TSSOP
4.4mm x 6.5mm x 0.925mm package body
G Package
Top View
854S057 Rev A 10/23/14
1
©2014 Integrated Device Technology, Inc.
854S057 DATA SHEET
Table 1. Pin Descriptions
Number
1, 20
2
3
4
5, 6
7
8
9
10, 11
12
13
14
15, 16
17
18
19
Name
V
DD
PCLK0
VT0
nPCLK0
SEL1, SEL0
PCLK1
VT1
nPCLK1
GND
nPCLK2
VT2
PCLK2
nQ, Q
nPCLK3
VT3
PCLK3
Power
Input
Input
Input
Input
Input
Input
Input
Power
Input
Input
Input
Output
Input
Input
Input
Pulldown
Type
Description
Power supply pins.
Non-inverting LVPECL differential clock input. R
T
= 50 termination to VT0.
Termination input. For LVDS input, leave floating. R
T
= 50 termination to VT0.
Inverting LVPECL differential clock input. R
T
= 50 termination to VT0.
Clock select inputs. LVCMOS/LVTTL interface levels.
Non-inverting LVPECL differential clock input. R
T
= 50 termination to VT1.
Termination input. For LVDS input, leave floating. R
T
= 50 termination to VT1.
Inverting LVPECL differential clock input. R
T
= 50 termination to VT1.
Power supply ground.
Inverting LVPECL differential clock input. R
T
= 50 termination to VT2.
Termination input. For LVDS input, leave floating. R
T
= 50 termination to VT2.
Non-inverting LVPECL differential clock input. R
T
= 50 termination to VT2.
Differential output pair. LVDS interface levels.
Inverting LVPECL differential clock input. R
T
= 50 termination to VT3.
Termination input. For LVDS input, leave floating. R
T
= 50 termination to VT3.
Non-inverting LVPECL differential clock input. R
T
= 50 termination to VT3.
NOTE:
Pulldown
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
Parameter
Input Capacitance
Test Conditions
Minimum
Typical
2
50
40
50
60
Maximum
Units
pF
k
R
PULLDOWN
Input Pulldown Resistor
R
T
Input Termination Resistor
Table 3. Control Input Function Table
Inputs
SEL1
0 (default)
0
1
1
SEL0
0 (default)
1
0
1
Outputs
PCLKx, nPCLKx
PCLK0, nPCLK0
PCLK1, nPCLK1
PCLK2, nPCLK2
PCLK3, nPCLK3
Rev A 10/23/14
2
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT
TERMINATION
854S057 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuos Current
Surge Current
Input Current, PCLK, nPCLK
V
T
Current, I
VT
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
±50mA
±100mA
92.1°C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
50
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
SEL0, SEL1
SEL0, SEL1
Test Conditions
V
DD
= 2.5V
V
DD
= 2.5V
V
DD
= V
IN
= 2.625V
V
DD
= 2.625V, V
IN
= 0V
-10
Minimum
1.7
-0.3
Typical
Maximum
V
DD
+ 0.3
0.7
150
Units
V
V
µA
µA
Table 4C. LVPECL Differential DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
I
IN
V
PP
V
CMR
Parameter
Absolute Input Current; NOTE 1
Peak-to-Peak Voltage
Common Mode Input Voltage; NOTE 2
Test Conditions
V
DD
= V
IN
= 2.625V
0.15
GND + 1.2
Minimum
Typical
Maximum
35
1.2
V
DD
Units
mA
V
V
NOTE 1: Guaranteed by design.
NOTE 2: Common mode input voltage is defined as V
IH
.
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT
TERMINATION
3
Rev A 10/23/14
854S057 DATA SHEET
Table 4D. LVDS DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OD
V
OD
V
OS
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.125
1.25
5
Test Conditions
Minimum
247
Typical
325
Maximum
454
50
1.375
50
Units
mV
mV
V
mV
Table 5. AC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
f
MAX
t
PD
tsk(pp)
tsk(i)
tjit
t
R
/ t
F
odc
Parameter
Output Frequency
Propagation Delay; NOTE 1
Part-to-Part Skew; NOTE 2, 3
Input Skew
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Output Rise/Fall Time
Output Duty Cycle
622.08MHz, Integration Range:
12kHz – 20MHz
20% to 80%
ƒ
700MHz
ƒ
1.1GHz
ƒ
2GHz
MUX
ISOLATION
MUX Isolation
ƒ = 500MHz
50
48
46
42
-65
0.047
250
52
54
58
150
Test Conditions
Minimum
Typical
Maximum
2
650
200
60
Units
GHz
ps
ps
ps
ps
ps
%
%
%
dBm
NOTE: All parameters measured at ƒ
2GHz unless noted otherwise.
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between different devices operating at the same supply voltage, same frequency and with equal load conditions.
Using the same type of inputs on each device, the output is measured at the differential cross point.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Rev A 10/23/14
4
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT
TERMINATION
854S057 DATA SHEET
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the
dBc Phase
Noise.
This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 622.08MHz
12kHz to 20MHz = 0.047ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
The source generator "Rohde & Schwarz SMA100A Low Noise
Signal Generator as external input to an Agilent 8133A 3GHz Pulse
Generator".
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT
TERMINATION
5
Rev A 10/23/14
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