– Utilizes advanced low-power design techniques to achieve low
typical power consumption
– Supports PCI Power Management Interface specification
(PCI-PM 1.1)
• Supports device power management states: D0, D3
hot
and
D3
cold
– Unused SerDes are disabled
Testability and Debug Features
– Ability to read and write any internal register via the SMBus
Sixteen General Purpose Input/Output Pins
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
Packaged in a 31mm x 31mm 500-ball BGA with 1mm ball
spacing
Product Description
Utilizing standard PCI Express interconnect, the PES32T8 provides
the most efficient I/O connectivity solution for applications requiring high
throughput, low latency, and simple board layout with a minimum
number of board layers. It provides connectivity for up to 8 ports across
32 integrated serial lanes. Each lane provides 2.5 Gbps of bandwidth in
both directions and is fully compliant with PCI Express Base specifica-
tion revision 1.1.
The PES32T8 is based on a flexible and efficient layered architec-
ture. The PCI Express layers consist of SerDes, Physical, Data Link and
Transaction layers. The PES32T8 can operate either as a store and
forward switch or a cut-through switch and is designed to switch
memory and I/O transactions. It supports eight Traffic Classes (TCs)
and one Virtual Channel (VC) with sophisticated resource management
to enable efficient switching and I/O connectivity.
Processor
Processor
North
Bridge
Memory
Memory
Memory
Memory
x8
PES32T8
x4
PCI Express
Slots
x4
x8
I/O
10GbE
x8
I/O
10GbE
I/O
SATA
I/O
SATA
Figure 2 I/O Expansion Application
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March 25, 2008
IDT 89PES32T8 Data Sheet
8-port
7-port
6-port
5-port
4-port
PCIe x8
PCIe x8
PCIe x8
PCIe x8
x8 upstream
PES32T8
PES32T8
PES32T8
PES32T8
x4 x4
x4 x4
x4 x4
x8
x4
x4
x4
x4
x8
x8
x4
x4
x8
x8
x8
PCIe x4
X4 upstream
PES32T8
x4 x4 x4 x4 x4 x4 x4
Figure 3 Configuration Options
Note:
The configurations in the above diagram show the maximum port widths. The PES32T8 can negotiate to narrower port widths — x4,
x2, or x1.
SMBus Interface
The PES32T8 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES32T8, allowing
every configuration register in the device to be read or written by an external agent. The master interface allows the default configuration register
values of the PES32T8 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used
by an external Hot-Plug I/O expander.
Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In
the slave interface, these address pins allow the SMBus address to which the device responds to be configured. In the master interface, these
address pins allow the SMBus address of the serial configuration EEPROM from which data is loaded to be configured. The SMBus address is set up
on negation of PERSTN by sampling the corresponding address pins. When the pins are sampled, the resulting address is assigned as shown in
Table 1.
Bit
1
2
3
4
5
6
7
Slave
SMBus
Address
SSMBADDR[1]
SSMBADDR[2]
SSMBADDR[3]
0
SSMBADDR[5]
1
1
Master
SMBus
Address
MSMBADDR[1]
MSMBADDR[2]
MSMBADDR[3]
MSMBADDR[4]
1
0
1
Table 1 Master and Slave SMBus Address Assignment
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March 25, 2008
IDT 89PES32T8 Data Sheet
As shown in Figure 4, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure
4(a), the master and slave SMBuses are tied together and the PES32T8 acts both as a SMBus master as well as a SMBus slave on this bus. This
requires that the SMBus master or processor that has access to PES32T8 registers supports SMBus arbitration. In some systems, this SMBus master
interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBus arbitration. To support
these systems, the PES32T8 may be configured to operate in a split configuration as shown in Figure 4(b).
In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is never required.
The PES32T8 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of the
serial EEPROM.
PES32T8
Processor
SMBus
Master
Serial
EEPROM
...
Other
SMBus
Devices
PES32T8
Processor
SMBus
Master
...
Other
SMBus
Devices
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
Serial
EEPROM
(a) Unified Configuration and Management Bus
(b) Split Configuration and Management Buses
Figure 4 SMBus Interface Configuration Examples
Hot-Plug Interface
The PES32T8 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES32T8
utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configura-
tion, whenever the state of a Hot-Plug output needs to be modified, the PES32T8 generates an SMBus transaction to the I/O expander with the new
value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin
(alternate function of GPIO) of the PES32T8. In response to an I/O expander interrupt, the PES32T8 generates an SMBus transaction to read the
state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
The PES32T8 provides 16 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin
may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These
alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.
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March 25, 2008
IDT 89PES32T8 Data Sheet
Pin Description
The following tables lists the functions of the pins provided on the PES32T8. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Signal
PE0RP[3:0]
PE0RN[3:0]
PE0TP[3:0]
PE0TN[3:0]
PE1RP[3:0]
PE1RN[3:0]
PE1TP[3:0]
PE1TN[3:0]
PE2RP[3:0]
PE2RN[3:0]
PE2TP[3:0]
PE2TN[3:0]
PE3RP[3:0]
PE3RN[3:0]
PE3TP[3:0]
PE3TN[3:0]
PE4RP[3:0]
PE4RN[3:0]
PE4TP[3:0]
PE4TN[3:0]
PE5RP[3:0]
PE5RN[3:0]
PE5TP[3:0]
PE5TN[3:0]
PE6RP[3:0]
PE6RN[3:0]
PE6TP[3:0]
PE6TN[3:0]
PE7RP[3:0]
PE7RN[3:0]
Type
I
O
I
Name/Description
PCI Express Port 0 Serial Data Receive.
Differential PCI Express receive
pairs for port 0. Port 0 is the upstream port.
PCI Express Port 0 Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port 0. Port 0 is the upstream port.
PCI Express Port 1 Serial Data Receive.
Differential PCI Express receive
pairs for port 1. When port 0 is merged with port 1, these signals become
port 0 receive pairs for lanes 4 through 7.
PCI Express Port 1 Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port 1. When port 0 is merged with port 1, these signals
become port 0 transmit pairs for lanes 4 through 7.
PCI Express Port 2 Serial Data Receive.
Differential PCI Express receive
pairs for port 2.
PCI Express Port 2 Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port 2.
PCI Express Port 3 Serial Data Receive.
Differential PCI Express receive
pairs for port 3. When port 2 is merged with port 3, these signals become
port 2 receive pairs for lanes 4 through 7.
PCI Express Port 3 Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port 3. When port 2 is merged with port 3, these signals
become port 2 transmit pairs for lanes 4 through 7.
PCI Express Port 4 Serial Data Receive.
Differential PCI Express receive
pairs for port 4.
PCI Express Port 4 Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port 4.
PCI Express Port 5 Serial Data Receive.
Differential PCI Express receive
pairs for port 5. When port 4 is merged with port 5, these signals become
port 4 receive pairs for lanes 4 through 7.
PCI Express Port 5 Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port 5. When port 4 is merged with port 5, these signals
become port 4 transmit pairs for lanes 4 through 7.
PCI Express Port 6 Serial Data Receive.
Differential PCI Express receive
pairs for port 6.
PCI Express Port 6 Serial Data Transmit.
Differential PCI Express trans-
mit pairs for port 6.
PCI Express Port 7 Serial Data Receive.
Differential PCI Express receive
pairs for port 7. When port 6 is merged with port 7, these signals become
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