DS1867E-10+ datasheet, PDF - EEWORLD Datasheet

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DS1867E-10+: DescriptionIC pot W/eeprom dual 10k 20tssop; CategoryAnalog mixed-signal IC converter; File Size308KB，14 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html; Environmental Compliance

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DS1867E-10+ Overview

IC pot W/eeprom dual 10k 20tssop

DS1867E-10+ Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Maxim
Parts packaging code	TSSOP
package instruction	0.173 INCH, ROHS COMPLIANT, TSSOP-20
Contacts	20
Reach Compliance Code	unknown
ECCN code	EAR99
Other features	OPERATE WITH SINGLE 5V SUPPLY
Nominal bandwidth	1 kHz
control interface	3-WIRE SERIAL
Converter type	DIGITAL POTENTIOMETER
JESD-30 code	R-PDSO-G20
JESD-609 code	e3
length	6.5 mm
Humidity sensitivity level	1
Nominal negative supply voltage	-5 V
Number of functions	2
Number of positions	256
Number of terminals	20
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP20,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
power supply	5 V
Certification status	Not Qualified
resistance law	LINEAR
Maximum resistor tolerance	20%
Maximum resistor terminal voltage	5.5 V
Minimum resistor terminal voltage	-5 V
Maximum seat height	1.1 mm
Nominal supply voltage	5 V
surface mount	YES
Nominal temperature coefficient	750 ppm/°C
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
Nominal total resistance	10000 Ω
width	4.4 mm

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DS1867

Dual Digital Potentiometer with EEPROM

www.dalsemi.com

FEATURES

Nonvolatile version of the popular DS1267

Low power consumption, quiet, pumpless

design

Operates from single 5V or

±5V

supplies

Two digitally controlled, 256-position

potentiometers

Wiper position is maintained in the absence of

power

Serial port provides means for setting and

reading both potentiometers

Resistors can be connected in series to

provide increased total resistance

16-pin SOIC and 20-pin TSSOP for surface

mount applications

Standard resistance values:

- DS1867-10 ~ 10 kΩ

- DS1867-50 ~ 50 kΩ

- DS1867-100 ~ 100 kΩ

Operating Temperature Range:

- Industrial: -40° to +85°

PIN ASSIGNMENT

RST

CLK

GND

OUT

14-Pin DIP (300-mil)

See Mech. Drawings Section

RST

CLK

GND

OUT

PIN DESCRIPTION

L0, L1

H0, H1

W1, W2

OUT

RST

16-Pin SOIC (300-mil)

CLK

OUT

GND

DNC

Low End of Resistor

High End of Resistor

Wiper End of Resistor

Substrate Bias

Wiper for Stacked Configuration

Serial Port Reset Input

Serial Port Data Input

Serial Port Clock Input

Cascade Serial Port Output

+5-Volt Supply Input

Ground

No Internal Connection

Do Not Connect

See Mech. Drawings Section

RST

CLK

DNC

GND

DNC

OUT

DNC

20-Pin TSSOP (173-mil)

See Mech. Drawings Section

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DS1867

DESCRIPTION

The DS1867 Dual Digital Potentiometer with EEPROM is the nonvolatile version of the popular DS1267

Dual Digital Potentiometer. The DS1867 consists of two digitally controlled potentiometers having 256-

position wiper settings. Wiper position is maintained in the absence of power through the use of

EEPROM memory cell arrays. Communication and control of the device are accomplished over a 3-wire

serial port which allows reads and writes of the wiper position. Both potentiometers can be stacked for

increased total resistance with the same resolution. For multiple-device, single-processor environments,

the DS1867 can be cascaded for control over a single 3-wire bus. The DS1867 is offered in three standard

resistance values.

OPERATION

The DS1867 contains two 256-position potentiometers whose wiper positions are set by an 8-bit value.

These two 8-bit values are written to a 17-bit I/O shift register which is used to store wiper position and

the stack select bit when the device is powered. An additional memory area, the shadow memory, stores

the 17-bit I/O shift register during a power-down sequence which provides for wiper nonvolatility. A

block diagram of the DS1867 is presented in Figure 1.

Communication and control of the DS1867 is accomplished through a 3-wire serial port interface that

drives an internal control logic unit. The 3-wire serial interface consists of the three input signals:

RST

CLK, and DQ.

The

RST

control signal is used to enable 3-wire serial port operation of the device. The

RST

signal is an

active high input and is required to begin any communication to the DS1867. The CLK signal input is

used to provide timing synchronization for data input and output. The DQ signal line is used to transmit

potentiometer wiper settings and the stack select bit configuration to the 17-bit I/O shift register of the

DS1867.

Figure 2(a) presents the 3-wire serial port protocol. As shown, the 3-wire port is inactive when the

RST

signal input is low. Communication with the DS1867 requires the transition of the

RST

input from a low

state to a high state. Once the 3-wire port has been activated, data is latched into the part on the low to

high transition of the CLK signal input. Three-wire serial timing requirements are provided in the timing

diagrams of Figure 2(b) and (c).

Data written to the DS1867 over the 3-wire serial interface is stored in the 17-bit I/O shift register (see

Figure 3). The 17-bit I/O shift register contains both 8-bit potentiometer wiper position values and the

stack select bit. The composition of the I/O shift register is presented in Figure 3. Bit 0 of the I/O shift

Configuration. Bits 1 through 8 of the I/O shift register contain the potentiometer-1 wiper position value.

Bit 1 will contain the MSB of the wiper setting for potentiometer-1 and bit 8 the LSB for the wiper

setting. Bits 9 through 16 of the I/O shift register contain the value of the potentiometer-0 wiper position

with the MSB for the wiper position occupying bit 9 and the LSB bit 16.

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DS1867

I/O SHIFT REGISTER

Figure 3

17-BIT I/O SHIFT REGISTER

Transmission of data always begins with the stack select bit followed by the potentiometer-1 wiper

position value and lastly the potentiometer-0 wiper position value (see Figure 2(a)).

When wiper position data is to be written to the DS1867, 17-bits (or some integer multiple) of data should

always be transmitted. Transactions which do not send a complete 17-bits (or multiple) will leave the

has been completed the

RST

signal input should be taken to a low state to prevent any inadvertent

changes to the device shift register. Once

RST

has reached a low state, the contents of the I/O shift

only engage pending a

RST

transition to the low state. The wiper position for the high-end terminals H0

and H1 will have data values FF (hex), while the low-end terminals will have data values 00 (hex).

STACKED CONFIGURATION

The potentiometers of the DS1867 can be connected in series as shown in Figure 4. This is referred to as

the stacked configuration and allows the user to double the total end-to-end resistance of the part. The

resolution of the combined potentiometers will remain the same as a single potentiometer but with a total

of 512 wiper positions available. Device resolution is defined as R

TOT

/256 (per potentiometer); where

TOT

is equal to the device resistance value. The wiper output for the combined stacked potentiometer will

be taken at the S

out

pin, which is the multiplexed output of the wiper of potentiometer-0 (W0) or

potentiometer-1 (W1). The potentiometer wiper selected at the S

out

output is governed by the setting of

the stack select bit (bit-0) of the 17-bit I/O shift register. If the stack select bit has value 0, the multiplexed

output, S

out

, will be that of the potentiometer-0 wiper. If the stack select bit has value 1, the multiplexed

output, S

out

, will be that of the potentiometer-1 wiper.

STACKED CONFIGURATION

Figure 4

CASCADE OPERATION

A feature of the DS1867 is the ability to control multiple devices from a single processor. Multiple

DS1867s can be linked or daisy-chained as shown in Figure 5. As a data bit is entered into the I/O shift

out

output after a maximum delay of 70 nanoseconds.

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