SX Microprocessor is an entry-level 32-bit CPU with a 16-bit external data bus and a 24-bit
external address bus The Intel386 SX CPU brings the vast software library of the Intel386
TM
Architecture to
entry-level systems It provides the performance benefits of a 32-bit programming architecture with the cost
savings associated with 16-bit hardware systems
240187 –47
Intel386
TM
SX Pipelined 32-Bit Microarchitecture
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copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT
INTEL CORPORATION 1995
January 1994
Order Number 240187-008
Intel386
TM
SX MICROPROCESSOR
Intel386
TM
SX MicroProcessor
CONTENTS
1 0 PIN DESCRIPTION
2 0 BASE ARCHITECTURE
2 1 Register Set
2 2 Instruction Set
2 3 Memory Organization
2 4 Addressing Modes
2 5 Data Types
2 6 I O Space
2 7 Interrupts and Exceptions
2 8 Reset and Initialization
2 9 Testability
2 10 Debugging Support
3 0 REAL MODE ARCHITECTURE
3 1 Memory Addressing
3 2 Reserved Locations
3 3 Interrupts
3 4 Shutdown and Halt
3 5 LOCK Operations
4 0 PROTECTED MODE
ARCHITECTURE
4 1 Addressing Mechanism
4 2 Segmentation
4 3 Protection
4 4 Paging
4 5 Virtual 8086 Environment
PAGE
3
6
6
10
11
12
15
15
17
20
20
21
22
22
23
23
23
23
24
24
24
29
33
36
CONTENTS
5 0 FUNCTIONAL DATA
5 1 Signal Description Overview
5 2 Bus Transfer Mechanism
5 3 Memory and I O Spaces
5 4 Bus Functional Description
5 5 Self-test Signature
5 6 Component and Revision
Identifiers
5 7 Coprocessor Interfacing
6 0 PACKAGE THERMAL
SPECIFICATIONS
7 0 ELECTRICAL SPECIFICATIONS
7 1 Power and Grounding
7 2 Maximum Ratings
7 3 D C Specifications
7 4 A C Specifications
7 5 Designing for ICE
TM
-Intel386 SX
Emulator
8 0 DIFFERENCES BETWEEN THE
Intel386
TM
SX CPU and the
Intel386
TM
DX CPU
9 0 INSTRUCTION SET
9 1 Intel386
TM
SX CPU Instruction
Encoding and Clock Count Summary
9 2 Instruction Encoding
PAGE
39
39
45
45
45
63
63
63
64
64
64
65
66
68
78
79
80
80
95
2
Intel386
TM
SX MICROPROCESSOR
1 0 PIN DESCRIPTION
240187 – 1
NOTE
NC
e
No Connect
Figure 1 1 Intel386
TM
SX Microprocessor Pin out Top View
Table 1 1 Alphabetical Pin Assignments
Address
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
A
20
A
21
A
22
A
23
18
51
52
53
54
55
56
58
59
60
61
62
64
65
66
70
72
73
74
75
76
79
80
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
10
D
11
D
12
D
13
D
14
D
15
Data
1
100
99
96
95
94
93
92
90
89
88
87
86
83
82
81
Control
ADS
BHE
BLE
BUSY
CLK2
D C
ERROR
FLT
HLDA
HOLD
INTR
LOCK
M IO
NA
NMI
PEREQ
READY
RESET
W R
16
19
17
34
15
24
36
28
3
4
40
26
23
6
38
37
7
33
25
N C
20
27
29
30
31
43
44
45
46
47
V
CC
8
9
10
21
32
39
42
48
57
69
71
84
91
97
V
SS
2
5
11
12
13
14
22
35
41
49
50
63
67
68
77
78
85
98
3
Intel386
TM
SX MICROPROCESSOR
1 0 PIN DESCRIPTION
(Continued)
The following are the Intel386
TM
SX Microprocessor pin descriptions The following definitions are used in the
pin descriptions
I
O
I O
-
The named signal is active LOW
Input signal
Output signal
Input and Output signal
No electrical connection
Symbol
CLK2
RESET
Type
I
I
15
33
Pin
Name and Function
CLK2
provides the fundamental timing for the Intel386 SX
Microprocessor For additional information see
Clock
RESET
suspends any operation in progress and places the
Intel386 SX Microprocessor in a known reset state See
Interrupt Signals
for additional information
Data Bus
inputs data during memory I O and interrupt
acknowledge read cycles and outputs data during memory and
I O write cycles See
Data Bus
for additional information
Address Bus
outputs physical memory or port I O addresses
See
Address Bus
for additional information
Write Read
is a bus cycle definition pin that distinguishes write
cycles from read cycles See
Bus Cycle Definition Signals
for
additional information
Data Control
is a bus cycle definition pin that distinguishes data
cycles either memory or I O from control cycles which are
interrupt acknowledge halt and code fetch See
Bus Cycle
Definition Signals
for additional information
Memory IO
is a bus cycle definition pin that distinguishes
memory cycles from input output cycles See
Bus Cycle
Definition Signals
for additional information
Bus Lock
is a bus cycle definition pin that indicates that other
system bus masters are not to gain control of the system bus
while it is active See
Bus Cycle Definition Signals
for
additional information
Address Status
indicates that a valid bus cycle definition and
address (W R D C M IO BHE BLE and A
23
– A
1
are
being driven at the Intel386 SX Microprocessor pins See
Bus
Control Signals
for additional information
Next Address
is used to request address pipelining See
Bus
Control Signals
for additional information
Bus Ready
terminates the bus cycle See
Bus Control Signals
for additional information
Byte Enables
indicate which data bytes of the data bus take part
in a bus cycle See
Address Bus
for additional information
D
15
– D
0
I O
81-83 86-90
92-96 99-100 1
80-79 76-72 70
66-64 62-58
56-51 18
25
A
23
– A
1
O
W R
O
D C
O
24
M IO
O
23
LOCK
O
26
ADS
O
16
NA
READY
BHE
BLE
I
I
O
6
7
19 17
4
Intel386
TM
SX MICROPROCESSOR
1 0 PIN DESCRIPTION
(Continued)
Symbol
HOLD
Type
I
4
Pin
Name and Function
Bus Hold Request
input allows another bus master to request
control of the local bus See
Bus Arbitration Signals
for
additional information
Bus Hold Acknowledge
output indicates that the Intel386 SX
Microprocessor has surrendered control of its local bus to
another bus master See
Bus Arbitration Signals
for additional
information
Interrupt Request
is a maskable input that signals the Intel386
SX Microprocessor to suspend execution of the current program
and execute an interrupt acknowledge function See
Interrupt
Signals
for additional information
Non-Maskable Interrupt Request
is a non-maskable input that
signals the Intel386 SX Microprocessor to suspend execution of
the current program and execute an interrupt acknowledge
function See
Interrupt Signals
for additional information
Busy
signals a busy condition from a processor extension See
Coprocessor Interface Signals
for additional information
Error
signals an error condition from a processor extension See
Coprocessor Interface Signals
for additional information
Processor Extension Request
indicates that the processor has
data to be transferred by the Intel386 SX Microprocessor See
Coprocessor Interface Signals
for additional information
Float
is an input which forces all bidirectional and output signals
including HLDA to the tri-state condition This allows the
electrically isolated Intel386SX PQFP to use ONCE (On-Circuit
Emulation) method without removing it from the PCB See
Float
for additional information
No Connects
should always be left unconnected Connection of
a N C pin may cause the processor to malfunction or be
incompatible with future steppings of the Intel386 SX
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