Freescale Semiconductor
Technical Data
MPC8555EEC
Rev. 4.2, 1/2008
MPC8555E PowerQUICC™ III
Integrated Communications Processor
Hardware Specification
The MPC8555E integrates a PowerPC™ processor core
built on Power Architecture™ technology with system logic
required for networking, telecommunications, and wireless
infrastructure applications. The MPC8555E is a member of
the PowerQUICC™ III family of devices that combine
system-level support for industry-standard interfaces with
processors that implement the embedded category of the
Power Architecture technology. For functional
characteristics of the processor, refer to the
MPC8555E
PowerQUICC™ III Integrated Communications Processor
Reference Manual.
To locate any published errata or updates for this document
refer to http://www.freescale.com or contact your Freescale
sales office.
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Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 8
Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 13
Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Ethernet: Three-Speed, MII Management . . . . . . . . . . 22
Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
CPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . . . 56
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
System Design Information . . . . . . . . . . . . . . . . . . . . . 78
Document Revision History . . . . . . . . . . . . . . . . . . . . 85
Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . 86
© Freescale Semiconductor, Inc., 2008. All rights reserved.
Overview
1
Overview
The following section provides a high-level overview of the MPC8555E features.
Figure 1
shows the
major functional units within the MPC8555E.
DDR
SDRAM
DDR SDRAM Controller
I
2
C Controller
DUART
GPIO
32b
IRQs
Local Bus Controller
Programmable
Interrupt Controller
CPM
Time-Slot Assigner
Serial
DMA
Security
Engine
256-Kbyte
L2 Cache/
SRAM
e500 Core
32-Kbyte L1
I Cache
32-Kbyte L1
D Cache
e500
Coherency
Module
Core Complex
Bus
64/32b PCI Controller
OCeaN
0/32b PCI Controller
DMA Controller
MPHY
UTOPIA
MIIs/RMIIs
TDMs
I/Os
FCC
FCC
SCC
SCC/USB
SCC
SMC
SMC
SPI
I
2
C
ROM
I-Memory
DPRAM
RISC
Engine
Parallel I/O
Baud Rate
Generators
Timers
CPM
Interrupt
Controller
Serial Interfaces
10/100/1000 MAC
10/100/1000 MAC
MII, GMII, TBI,
RTBI, RGMIIs
Figure 1. MPC8555E Block Diagram
1.1
Key Features
The following lists an overview of the MPC8555E feature set.
• Embedded e500 Book E-compatible core
— High-performance, 32-bit Book E-enhanced core that implements the PowerPC architecture
— Dual-issue superscalar, 7-stage pipeline design
— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection
— Lockable L1 caches—entire cache or on a per-line basis
— Separate locking for instructions and data
— Single-precision floating-point operations
— Memory management unit especially designed for embedded applications
— Enhanced hardware and software debug support
— Dynamic power management
— Performance monitor facility
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
2
Freescale Semiconductor
Overview
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•
Security Engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,
IEEE Std 802.11i™, iSCSI, and IKE processing. The Security Engine contains 4 Crypto-channels,
a Controller, and a set of crypto Execution Units (EUs). The Execution Units are:
— Public Key Execution Unit (PKEU) supporting the following:
– RSA and Diffie-Hellman
– Programmable field size up to 2048-bits
– Elliptic curve cryptography
– F2m and F(p) modes
– Programmable field size up to 511-bits
— Data Encryption Standard Execution Unit (DEU)
– DES, 3DES
– Two key (K1, K2) or Three Key (K1, K2, K3)
– ECB and CBC modes for both DES and 3DES
— Advanced Encryption Standard Unit (AESU)
– Implements the Rinjdael symmetric key cipher
– Key lengths of 128, 192, and 256 bits.Two key
– ECB, CBC, CCM, and Counter modes
— ARC Four execution unit (AFEU)
– Implements a stream cipher compatible with the RC4 algorithm
– 40- to 128-bit programmable key
— Message Digest Execution Unit (MDEU)
– SHA with 160-bit or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either algorithm
— Random Number Generator (RNG)
— 4 Crypto-channels, each supporting multi-command descriptor chains
– Static and/or dynamic assignment of crypto-execution units via an integrated controller
– Buffer size of 256 Bytes for each execution unit, with flow control for large data sizes
High-performance RISC CPM operating at up to 333 MHz
— CPM software compatibility with previous PowerQUICC families
— One instruction per clock
— Executes code from internal ROM or instruction RAM
— 32-bit RISC architecture
— Tuned for communication environments: instruction set supports CRC computation and bit
manipulation.
— Internal timer
— Interfaces with the embedded e500 core processor through a 32-Kbyte dual-port RAM and
virtual DMA channels for each peripheral controller
— Handles serial protocols and virtual DMA
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
3
Overview
•
— Two full-duplex fast communications controllers (FCCs) that support the following protocols:
– ATM protocol through two UTOPIA level 2 interfaces
– IEEE Std 802.3™/Fast Ethernet (10/100)
– HDLC
– Totally transparent operation
— Three full-duplex serial communications controllers (SCCs) support the following protocols:
– High level/synchronous data link control (HDLC/SDLC)
– LocalTalk (HDLC-based local area network protocol)
– Universal asynchronous receiver transmitter (UART)
– Synchronous UART (1x clock mode)
– Binary synchronous communication (BISYNC)
– Totally transparent operation
– QMC support, providing 64 channels per SCC using only one physical TDM interface
— Universal serial bus (USB) controller that is full/low-speed compliant (multiplexed on an SCC)
– USB host mode
– Supports USB slave mode
— Serial peripheral interface (SPI) support for master or slave
— I
2
C bus controller
— Two serial management controllers (SMCs) supporting:
– UART
– Transparent
– General-circuit interfaces (GCI)
— Time-slot assigner supports multiplexing of data from any of the SCCs and FCCs onto eight
time-division multiplexed (TDM) interfaces. The time-slot assigner supports the following
TDM formats:
– T1/CEPT lines
– T3/E3
– Pulse code modulation (PCM) highway interface
– ISDN primary rate
– Freescale interchip digital link (IDL)
– General circuit interface (GCI)
— User-defined interfaces
— Eight independent baud rate generators (BRGs)
— Four general-purpose 16-bit timers or two 32-bit timers
— General-purpose parallel ports—16 parallel I/O lines with interrupt capability
256 Kbytes of on-chip memory
— Can act as a 256-Kbyte level-2 cache
— Can act as a 256-Kbyte or two 128-Kbyte memory-mapped SRAM arrays
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
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Freescale Semiconductor
Overview
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•
Can be partitioned into 128-Kbyte L2 cache plus 128-Kbyte SRAM
Full ECC support on 64-bit boundary in both cache and SRAM modes
SRAM operation supports relocation and is byte-accessible
Cache mode supports instruction caching, data caching, or both
External masters can force data to be allocated into the cache through programmed memory
ranges or special transaction types (stashing).
— Eight-way set-associative cache organization (1024 sets of 32-byte cache lines)
— Supports locking the entire cache or selected lines
– Individual line locks set and cleared through Book E instructions or by externally mastered
transactions
— Global locking and flash clearing done through writes to L2 configuration registers
— Instruction and data locks can be flash cleared separately
— Read and write buffering for internal bus accesses
Address translation and mapping unit (ATMU)
— Eight local access windows define mapping within local 32-bit address space
— Inbound and outbound ATMUs map to larger external address spaces
– Three inbound windows plus a configuration window on PCI
– Four inbound windows
– Four outbound windows plus default translation for PCI
DDR memory controller
— Programmable timing supporting first generation DDR SDRAM
— 64-bit data interface, up to MHz data rate
— Four banks of memory supported, each up to 1 Gbyte
— DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports
— Full ECC support
— Page mode support (up to 16 simultaneous open pages)
— Contiguous or discontiguous memory mapping
— Sleep mode support for self refresh DDR SDRAM
— Supports auto refreshing
— On-the-fly power management using CKE signal
— Registered DIMM support
— Fast memory access via JTAG port
— 2.5-V SSTL2 compatible I/O
Programmable interrupt controller (PIC)
— Programming model is compliant with the OpenPIC architecture
— Supports 16 programmable interrupt and processor task priority levels
— Supports 12 discrete external interrupts
— Supports 4 message interrupts with 32-bit messages
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
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