Freescale Semiconductor, Inc.
Advance Information
MPC8560PB
Rev. 0, 12/2003
MPC8560 PowerQUICC III™
Integrated Communications
Processor Product Brief
Freescale Semiconductor, Inc...
The MPC8560 PowerQUICC III™ is a next-generation PowerQUICC II™ integrated
communications processor. The MPC8560 integrates the processing power for networking
and communications peripherals. resulting in higher device performance. The MPC8560
contains an embedded PowerPC™ core. The MPC8560 is a member of a growing family of
products that combine system-level support for industry standard interfaces to processors that
implement the PowerPC architecture. This chapter provides a high-level description of the
features and functionality of the MPC8560 integrated microprocessor.
Part I Introduction
Motorola’s leading PowerQUICC III architecture integrates two processing blocks—a
high-performance embedded e500 core and the communications processor module (CPM).
The e500 core implements the enhanced Book E instruction set architecture and provides
unprecedented levels of hardware and software debugging support.
The CPM of the MPC8560 supports 3 fast serial communications channels (FCCs) for
155-Mbps ATM and fast Ethernet and up to 256 full-duplex, time-division-multiplexed
(TDM) channels using 2 multi-channel controllers (MCCs). In addition, the CPM supports
four serial communications controllers (SCCs), one serial peripheral interface (SPI), and one
I
2
C interface.
In addition, the MPC8560 offers 256 Kbytes of L2 cache, 2 integrated 10/100/1Gb three-speed
Ethernet controllers (TSECs), a DDR SDRAM memory controller, a 64-bit PCI/PCI-X
controller, an 8-bit RapidIO port, a programmable interrupt controller, an I
2
C controller, a
4-channel DMA controller, and a general-purpose I/O port. The high level of integration in the
MPC8560 simplifies board design and offers significant bandwidth and performance for
high-end control-plane and data-plane applications.
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Key Features
Part II MPC8560 Overview
The following section provides a high-level overview of the features of the MPC8560.
Figure 1 shows the major functional units in the MPC8560.
256-Kbyte
L2 Cache/
SRAM
e500 Core
e500
Coherency
Module
32-Kbyte L1
Instruction
Cache
32-Kbyte
L1 Data
Cache
DDR
SDRAM
DDR Memory Controller
I
2
C Interface
GPIO
32b
Local Bus Controller
Programmable Interrupt
Controller
CPM
Core Complex
Bus
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IRQs
SDMA
Channels
ROM
I-Memory
DPRAM
RISC
Engine
Parallel IO
Baud-Rate
Generators
(BRGs)
CPM Timers
CPM
Interrupt
Controller
OCeaN
Switch
Fabric
MPHY
UTOPIAs
TC-Layer
Time-Slot Assigner
Time-Slot Assigner
RapidIO Interface
PCI/PCI-X Bus
Interface
4-Channel DMA
Controller
10/100/1Gb MAC
10/100/1Gb MAC
MCC
MCC
FCC
FCC
FCC
SCC
SCC
SCC
SCC
SPI
I
2
C
RapidIO-8
16 Gb/s
PCI-X 64b
133 MHz
TDMs
Serial Interface
MIIs/RMIIs
MII, GMII, TBI,
RTBI, RGMIIs
I/Os
Figure 1. MPC8560 Block Diagram
2.1
•
Key Features
High-performance, 32-bit Book E–enhanced core that implements the PowerPC architecture
— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can
be locked entirely or on a per-line basis, with separate locking for instructions and data.
— Signal-processing engine (SPE) auxiliary processing unit (APU) provides an extensive
instruction set for vector (64-bit) integer, single-precision floating-point, and fractional
operations. These instructions use both the upper and lower words of the 64-bit GPRs as they
are defined by the SPE APU.
The following is an overview of the MPC8560 feature set.
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MPC8560 PowerQUICC III™
Integrated Communications Processor Product Brief
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Key Features
•
— The single-precision floating-point (SPFP) APU provides an instruction set for single-precision
(32-bit) floating-point instructions.
— Memory management unit (MMU) especially designed for embedded applications
— Enhanced hardware and software debug support
— Performance monitor facility (similar to but different from the MPC8560 performance monitor
described in the
MPC8560 PowerQUICC III Integrated Communications Processor Reference
Manual.)
The e500 defines features that are not implemented on the MPC8560. It also generally defines some
features that the MPC8560 implements more specifically. An understanding of these differences
can be critical to ensure proper operation. These differences are summarized in Section 5.14,
“MPC8560 Implementation Details,” in the reference manual.
Section 3.1, “e500 Core Overview,” in the reference manual includes a comprehensive list of e500
core features.
High-performance RISC CPM operating at up to 333 MHz
— CPM software compatibility with previous PowerQUICC families
— One instruction per clock
— Executes code from internal ROM or instruction RAM
— 32-bit RISC architecture
— Tuned for communication environments—Instruction set supports CRC computation and bit
manipulation
— Internal timer
— Interfaces with the embedded e500 core processor through a 32-Kbyte dual-port RAM and
virtual DMA channels for each peripheral controller
— Handles serial protocols and virtual DMA
— Three full-duplex fast serial communications controllers (FCCs) that support the following
protocols:
– ATM protocol through UTOPIA interface (FCC1 and FCC2 only)
– IEEE802.3/fast Ethernet
– HDLC
– Totally transparent operation
— Two multi-channel controllers (MCCs) that together can handle up to 256 HDLC/transparent
channels at 64 Kbps each, multiplexed on up to 8 TDM interfaces
— Four full-duplex serial communications controllers (SCCs) that support the following
protocols:
– High level/synchronous data link control (HDLC/SDLC)
– LocalTalk (HDLC-based local area network protocol)
– Universal asynchronous receiver transmitter (UART)
– Synchronous UART (1x clock mode)
– Binary synchronous communication (BISYNC)
– Totally transparent operation
— Serial peripheral interface (SPI) support for master or slave
— I
2
C bus controller
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MPC8560 PowerQUICC III™
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Key Features
•
•
— Time-slot assigner (TSA) supports multiplexing of data from any of the SCCs and FCCs onto
eight time-division multiplexed (TDM) interfaces. The time-slot assigner supports the
following TDM formats:
– T1/CEPT lines
– T3/E3
– Pulse code modulation (PCM) highway interface
– ISDN primary rate
– Motorola interchip digital link (IDL)
– General circuit interface (GCI)
— User-defined interfaces
— Eight independent baud rate generators (BRGs)
— Four general-purpose 16-bit timers or two 32-bit timers
— General-purpose parallel ports—16 parallel I/O lines with interrupt capability
— Supports inverse muxing of ATM cells (IMA)
256-Kbyte L2 cache/SRAM
— Can be configured as follows:
– Full cache mode (256-Kbyte cache)
– Full memory-mapped SRAM mode (256-Kbyte SRAM mapped as a single 256-Kbyte block
or two 128-Kbyte blocks)
– Half SRAM and half cache mode (128-Kbyte cache and 128-Kbyte memory-mapped
SRAM)
— Full error checking and correction (ECC) support on 64-bit boundary in both cache and SRAM
modes
— Cache mode supports instruction caching, data caching, or both
— External masters can force data to be allocated into the cache through programmed memory
ranges or special transaction types (stashing).
— Eight-way set-associative cache organization (1024 sets of 32-byte cache lines)
— Supports locking the entire cache or selected lines. Individual line locks are set and cleared
through Book E instructions or by externally mastered transactions.
— Global locking and flash clearing done through writes to L2 configuration registers
— Instruction and data locks can be flash cleared separately
— Read and write buffering for internal bus accesses
— SRAM features include the following:
– I/O devices access SRAM regions by marking transactions as snoopable (global).
– Regions can reside at any aligned location in the memory map.
– Byte-accessible ECC is protected using read-modify-write transactions accesses for smaller
than cache-line accesses
Address translation and mapping unit (ATMU)
— Eight local access windows define mapping within local 32-bit address space
— Inbound and outbound ATMUs map to larger external address spaces
– Three inbound windows plus a configuration window on PCI/PCI-X
– Four inbound windows plus a default and configuration window on RapidIO
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MPC8560 PowerQUICC III™
Integrated Communications Processor Product Brief
For More Information On This Product,
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Go to: www.freescale.com
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Key Features
•
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•
•
– Four outbound windows plus default translation for PCI
– Eight outbound windows plus default translation for RapidIO
DDR memory controller
— Programmable timing supporting DDR-1 SDRAM
— 64-bit data interface, up to 333-MHz data rate
— Four banks of memory supported, each up to 1 Gbyte
— DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports
— Full ECC support
— Page mode support (up to 16 simultaneous open pages)
— Contiguous or discontiguous memory mapping
— Read-modify-write support for RapidIO atomic increment, decrement, set, and clear
transactions
— Sleep mode support for self-refresh SDRAM
— Supports auto refreshing
— On-the-fly power management using CKE signal
— Registered DIMM support
— Fast memory access through JTAG port
— 2.5-V SSTL2 compatible I/O
RapidIO interface unit
— 8-bit RapidIO I/O and messaging protocols
— Source-synchronous double data rate (DDR) interfaces
— Supports small type systems (small domain, 8-bit device ID)
— Supports four priority levels (ordering within a level)
— Reordering across priority levels
— Maximum data payload of 256 bytes per packet
— Packet pacing support at the physical layer
— CRC protection for packets
— Supports atomic operations increment, decrement, set, and clear
— LVDS signaling
RapidIO–compliant message unit
— One inbound data message structure (inbox)
— One outbound data message structure (outbox)
— Supports chaining and direct modes in the outbox
— Support of up to 16 packets per message
— Support of up to 256 bytes per packet and up to 4 Kbytes of data per message
— Supports one inbound doorbell message structure
Programmable interrupt controller (PIC)
— Programming model is compliant with the OpenPIC architecture.
— Supports 16 programmable interrupt and processor task priority levels
— Supports 12 discrete external interrupts
•
MOTOROLA
MPC8560 PowerQUICC III™
Integrated Communications Processor Product Brief
For More Information On This Product,
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Go to: www.freescale.com
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