Freescale Semiconductor
Technical Data
Document Number: MPC8358EEC
Rev. 3, 01/2011
MPC8358E
PowerQUICC II Pro Processor
Revision 2.1 PBGA Silicon
Hardware Specifications
This document provides an overview of the MPC8358E
PowerQUICC II Pro processor revision 2.1 PBGA features,
including a block diagram showing the major functional
components. This device is a cost-effective, highly
integrated communications processor that addresses the
needs of the networking, wireless infrastructure, and
telecommunications markets. Target applications include
next generation DSLAMs, network interface cards for 3G
base stations (Node Bs), routers, media gateways, and high
end IADs. The device extends current PowerQUICC II Pro
offerings, adding higher CPU performance, additional
functionality, faster interfaces, and robust interworking
between protocols while addressing the requirements related
to time-to-market, price, power, and package size. This
device can be used for the control plane and also has data
plane functionality.
For functional characteristics of the processor, refer to the
MPC8360E PowerQUICC II Pro Integrated
Communications Processor Family Reference Manual,
Rev. 3.
To locate any updates for this document, refer to the
MPC8360E product summary page on our website listed on
the back cover of this document or contact your Freescale
sales office.
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Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Electrical Characteristics . . . . . . . . . . . . . . . . . . 7
Power Characteristics . . . . . . . . . . . . . . . . . . . 12
Clock Input Timing . . . . . . . . . . . . . . . . . . . . . 13
RESET Initialization . . . . . . . . . . . . . . . . . . . . 15
DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . 18
DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
UCC Ethernet Controller: Three-Speed Ethernet,
MII Management . . . . . . . . . . . . . . . . . . . . . . . 25
Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
I
2
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
UTOPIA/POS . . . . . . . . . . . . . . . . . . . . . . . . . 59
HDLC, BISYNC, Transparent, and Synchronous
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Package and Pin Listings . . . . . . . . . . . . . . . . . 65
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
System Design Information . . . . . . . . . . . . . . . 89
Ordering Information . . . . . . . . . . . . . . . . . . . . 92
Document Revision History . . . . . . . . . . . . . . 94
© 2011 Freescale Semiconductor, Inc. All rights reserved.
Overview
1
Overview
This section describes a high-level overview including features and general operation of the MPC8358E
PowerQUICC II Pro processor. A major component of this device is the e300 core, which includes
32 Kbytes of instruction and data cache and is fully compatible with the Power Architecture™ 603e
instruction set. The new QUICC Engine module provides termination, interworking, and switching
between a wide range of protocols including ATM, Ethernet, HDLC, and POS. The QUICC Engine
module’s enhanced interworking eases the transition and reduces investment costs from ATM to IP based
systems. The MPC8358E has a single DDR SDRAM memory controller. The MPC8358E also offers a
32-bit PCI controller, a flexible local bus, and a dedicated security engine.
Figure 1
shows the MPC8358E block diagram.
e300 Core
32KB
I-Cache
32KB
D-Cache
Security Engine
System Interface Unit
(SIU)
Memory Controllers
GPCM/UPM/SDRAM
32/64 DDR Interface Unit
PCI Bridge
Local Bus
Bus Arbitration
Multi-User
RAM
DUART
Serial DMA
&
2 Virtual
DMAs
Dual I2C
4 Channel DMA
Interrupt Controller
UCC1
UCC2
UCC3
UCC4
UCC5
UCC8
SPI1
SPI2
USB
Protection & Configuration
System Reset
Clock Synthesizer
DDRC
PCI
Local
Classic G2 MMUs
FPU
JTAG/COP
Power
Management
Timers
QUICC Engine Module
Baud Rate
Generators
Parallel I/O
Accelerators
Dual 32-Bit RISC CP
Time Slot Assigner
Serial Interface
4 TDM Ports
6 MII/
RMII
2 GMII/
RGMII/TBI/RTBI
1 UTOPIA/POS
(31/124 MPHY)
Figure 1. MPC8358E Block Diagram
Major features of the MPC8358E are as follows:
• e300 PowerPC processor core (enhanced version of the MPC603e core)
— Operates at up to 400 MHz (for the MPC8358E)
— High-performance, superscalar processor core
— Floating-point, integer, load/store, system register, and branch processing units
MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
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Freescale Semiconductor
Overview
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•
32-Kbyte instruction cache, 32-Kbyte data cache
Lockable portion of L1 cache
Dynamic power management
Software-compatible with the Freescale processor families implementing the Power
Architecture™ technology
QUICC Engine unit
— Two 32-bit RISC controllers for flexible support of the communications peripherals, each
operating up to 400 MHz (for the MPC8358E)
— Serial DMA channel for receive and transmit on all serial channels
— QUICC Engine module peripheral request interface (for SEC, PCI, IEEE Std. 1588™)
— Six UCCs on the MPC8358E supporting the following protocols and interfaces (not all of them
simultaneously):
– IEEE 1588 protocol supported
– 10/100 Mbps Ethernet/IEEE Std. 802.3™ CDMA/CS interface through a
media-independent interface (MII, RMII, RGMII)
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– 1000 Mbps Ethernet/IEEE 802.3 CDMA/CS interface through a media-independent
interface (GMII, RGMII, TBI, RTBI) on UCC1 and UCC2
– 9.6-Kbyte jumbo frames
– ATM full-duplex SAR, up to 622 Mbps (OC-12/STM-4), AAL0, AAL1, and AAL5 in
accordance ITU-T I.363.5
– ATM AAL2 CPS, SSSAR, and SSTED up to 155 Mbps (OC-3/STM-1) Mbps full duplex
(with 4 CPS packets per cell) in accordance ITU-T I.366.1 and I.363.2
– ATM traffic shaping for CBR, VBR, UBR, and GFR traffic types compatible with ATM
forum TM4.1 for up to 64-Kbyte simultaneous ATM channels
– ATM AAL1 structured and unstructured circuit emulation service (CES 2.0) in accordance
with ITU-T I.163.1 and ATM Forum af-vtoa-00-0078.000
– IMA (Inverse Multiplexing over ATM) for up to 31 IMA links over 8 IMA groups in
accordance with the ATM forum AF-PHY-0086.000 (Version 1.0) and AF-PHY-0086.001
(Version 1.1)
– ATM Transmission Convergence layer support in accordance with ITU-T I.432
– ATM OAM handling features compatible with ITU-T I.610
– PPP, Multi-Link (ML-PPP), Multi-Class (MC-PPP) and PPP mux in accordance with the
following RFCs: 1661, 1662, 1990, 2686, and 3153
– IP support for IPv4 packets including TOS, TTL, and header checksum processing
– Ethernet over first mile IEEE 802.3ah
– Shim header
– Ethernet-to-Ethernet/AAL5/AAL2 inter-working
– L2 Ethernet switching using MAC address or IEEE Std. 802.1P/Q™ VLAN tags
1.SMII or SGMII media-independent interface is not currently supported.
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Overview
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– ATM (AAL2/AAL5) to Ethernet (IP) interworking in accordance with RFC2684 including
bridging of ATM ports to Ethernet ports
– Extensive support for ATM statistics and Ethernet RMON/MIB statistics
– AAL2 protocol rate up to 4 CPS at OC-3/STM-1 rate
– Packet over Sonet (POS) up to 622-Mbps full-duplex 124 MultiPHY
– POS hardware; microcode must be loaded as an IRAM package
– Transparent up to 70-Mbps full-duplex
– HDLC up to 70-Mbps full-duplex
– HDLC BUS up to 10 Mbps
– Asynchronous HDLC
– UART
– BISYNC up to 2 Mbps
– User-programmable Virtual FIFO size
– QUICC multichannel controller (QMC) for 64 TDM channels
— One UTOPIA/POS interface on the MPC8358E supporting 31/124 MultiPHY
— Two serial peripheral interfaces (SPI); SPI2 is dedicated to Ethernet PHY management
— Four TDM interfaces on the MPC8358E with 1-bit mode for E3/T3 rates in clear channel
— Sixteen independent baud rate generators and 30 input clock pins for supplying clocks to UCC
serial channels
— Four independent 16-bit timers that can be interconnected as four 32-bit timers
— Interworking functionality:
– Layer 2 10/100-Base T Ethernet switch
– ATM-to-ATM switching (AAL0, 2, 5)
– Ethernet-to-ATM switching with L3/L4 support
– PPP interworking
Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,
802.11i®, iSCSI, and IKE processing. The security engine contains four crypto-channels, a
controller, and a set of crypto execution units (EUs).
— Public key execution unit (PKEU) supporting the following:
– RSA and Diffie-Hellman
– Programmable field size up to 2048 bits
– Elliptic curve cryptography
– F2m and F(p) modes
– Programmable field size up to 511 bits
— Data encryption standard execution unit (DEU)
– DES, 3DES
– Two key (K1, K2) or three key (K1, K2, K3)
– ECB and CBC modes for both DES and 3DES
MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
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Freescale Semiconductor
Overview
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— Advanced encryption standard unit (AESU)
— Implements the Rinjdael symmetric key cipher
— Key lengths of 128, 192, and 256 bits, two key
– ECB, CBC, CCM, and counter modes
— ARC four execution unit (AFEU)
– Implements a stream cipher compatible with the RC4 algorithm
– 40- to 128-bit programmable key
— Message digest execution unit (MDEU)
– SHA with 160-, 224-, or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either SHA or MD5 algorithm
— Random number generator (RNG)
— Four crypto-channels, each supporting multi-command descriptor chains
– Static and/or dynamic assignment of crypto-execution units via an integrated controller
– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
— Storage/NAS XOR parity generation accelerator for RAID applications
DDR SDRAM memory controller on the MPC8358E
— Programmable timing supporting both DDR1 and DDR2 SDRAM
— On the MPC8358E, the DDR bus can be configured as a 32- or 64-bit bus
— 32- or 64-bit data interface, up to 266 MHz (for the MPC8358E) data rate
— Four banks of memory, each up to 1 Gbyte
— DRAM chip configurations from 64 Mbits to 1 Gigabit with ×8/×16 data ports
— Full ECC support
— Page mode support (up to 16 simultaneous open pages for DDR1, up to 32 simultaneous open
pages for DDR2)
— Contiguous or discontiguous memory mapping
— Read-modify-write support
— Sleep mode support for self refresh SDRAM
— Supports auto refreshing
— Supports source clock mode
— On-the-fly power management using CKE
— Registered DIMM support
— 2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2
— External driver impedance calibration
— On-die termination (ODT)
PCI interface
— PCI Specification Revision 2.3 compatible
MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
Freescale Semiconductor
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