531UB1085M00DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 531UB1085M00DG

531UB1085M00DG: DescriptionCMOS/TTL Output Clock Oscillator, 1085MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531UB1085M00DG Overview

CMOS/TTL Output Clock Oscillator, 1085MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531UB1085M00DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	20%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	1085 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS/TTL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	2.75 V
Minimum supply voltage	2.25 V
Nominal supply voltage	2.5 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

Bole brand BCD-185C refrigerator circuit

Power supply low voltage circuit breaker circuit diagram

The output voltage is 1.3V-9V power supply circuit diagram

AN7161N power amplifier circuit diagram

Current mode circuit diagram

Gas smoke alarm 3

Please recommend a Linux development board for beginners (with complete supporting information): I want to learn Linux recently, so I bought a book called "Embedded Linux Application Development" by Wei Dongshan. The development board for this book is S3C2410/S3C2440, but it is embarrassing that ...; 火火山 Linux and Android

"Field Effect Transistor Comparison Table" and "Appearance and Pin Arrangement Diagram": In the field effect transistor comparison table, junction field effect transistors (JFET), metal oxide semiconductor field effect transistors (MOSFET), Schottky barrier controlled gate field effect tr...; fighting Test/Measurement

MSP430FG4619 has communication problems with LCD through usci_spi, please help: Hello everyone, this is my first time using such a high-end chip as MSP430FG4619, and my first time making LCD products. I don't understand many things, please give me some advice. I have some problem...; chenc_44 Microcontroller MCU

cpld\fpga\verilog hdl video tutorial: cpld\fpga\verilog hdl video tutorials: Getting Started: Lecture 1, FPGA Design Fundamentals (PDF, video) Lecture 2, FPGA Design Getting Started (video, homework) Lecture 3: Verilog HDL Fundamentals (P...; 676797119 FPGA/CPLD

Merkel presents Xi Jinping with a map of China drawn by Germany in 1735 (Photo): Please see the link: [url]http://news.sohu.com/20140330/n397448032.shtml[/url] Does anyone have a detailed introduction to this map? Where can I find a clear picture like the one on TV?...; wangfuchong Talking

How good is EXP430FR5739?: How good is 430FR5739? I think I need to test it. So posting is a must....; mcu430 Microcontroller MCU

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components