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54FCT573CTLBG

Description
Bus Driver
Categorylogic    logic   
File Size52KB,7 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
Download Datasheet Parametric View All

54FCT573CTLBG Overview

Bus Driver

54FCT573CTLBG Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
package instructionQCCN,
Reach Compliance Codecompliant
Other featuresBROADSIDE VERSION OF 373
seriesFCT
JESD-30 codeS-XQCC-N20
Logic integrated circuit typeBUS DRIVER
Number of digits8
Number of functions1
Number of ports2
Number of terminals20
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialUNSPECIFIED
encapsulated codeQCCN
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)260
propagation delay (tpd)8 ns
Filter levelMIL-STD-883 Class B
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal formNO LEAD
Terminal locationQUAD
Maximum time at peak reflow temperature30
Base Number Matches1
IDT54/74FCT573T/AT/CT
FAST CMOS OCTAL TRANSPARENT LATCH
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
FAST CMOS OCTAL
TRANSPARENT LATCH
IDT54/74FCT573T/AT/CT
FEATURES:
Std., A, and C grades
Low input and output leakage
1µA (max.)
CMOS power levels
True TTL input and output compatibility:
– V
OH
= 3.3V (typ.)
– V
OL
= 0.3V (typ.)
High Drive outputs (-15mA I
OH
, 48mA I
OL
)
Meets or exceeds JEDEC standard 18 specifications
Military product compliant to MIL-STD-883, Class B and DESC
listed (dual marked)
Power off disable outputs permit "live insertion"
Available in the following packages:
– Industrial: SOIC, QSOP
– Military: CERDIP, LCC
DESCRIPTION:
The FCT573Tis an octal transparent latch built using an advanced dual
metal CMOS technology. These octal latches have 3-state outputs and are
intended for bus oriented applications. The flip-flops appear transparent to
the data when Latch Enable (LE) is high. When LE is low, the data that meets
the set-up time is latched. Data appears on the bus when the Output Enable
(OE) is low. When
OE
is high, the bus output is in the high-impedance state.
FUNCTIONAL BLOCK DIAGRAM
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
O
G
D
O
G
D
O
G
D
O
G
D
O
G
D
O
G
D
O
G
D
O
G
LE
OE
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
1
NOVEMBER 2016
DSC-5948/8
© 2016 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.

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