Agilent AT-32063
Low Current, High Performance
NPN Silicon Bipolar Transistor
Data Sheet
Features
• High Performance Bipolar
Transistor Optimized for
Low Current, Low Voltage
Operation
• 900 MHz Performance:
1.1 dB NF, 14.5 dB G
A
• Characterized for End-of-
Life Battery Use (2.7 V)
• SOT-363 (SC-70) Plastic
Package
• Tape-and-Reel Packaging
Option Available
Description
The AT-32063 contains two high
performance NPN bipolar transis-
tors in a single SOT-363 package.
The devices are unconnected,
allowing flexibility in design. The
pin-out is convenient for cascode
amplifier designs. The SOT-363
package is an industry standard
plastic surface mount package.
The 3.2 micron emitter-to-emitter
pitch and reduced parasitic design
of the transistor yields extremely
high performance products that
can perform a multiplicity of
tasks. The 20 emitter finger
interdigitated geometry yields a
transistor that is easy to match to
and extremely fast, with moderate
power, low noise resistance, and
low operating currents.
Optimized performance at 2.7 V
makes this device ideal for use in
900 MHz, 1.8 GHz, and 2.4 GHz
battery operated systems as an
LNA, gain stage, buffer, oscillator,
or active mixer. Typical amplifier
designs at 900 MHz yield 1.3 dB
noise figures with 12 dB or more
associated gain at a 2.7 V, 5 mA
bias, with noise performance
being relatively insensitive to
input match. High gain capability
at 1 V, 1 mA makes this device a
good fit for 900 MHz pager appli-
cations. Voltage breakdowns are
high enough for use at 5 volts.
Surface Mount Package
SOT-363 (SC-70)
Pin Connections and
Package Marking
1
B
1
2
E
1
3
C
2
4
B
2
5
E
2
6
C
1
I
I
• Lead-free Option Available
The AT-3 series bipolar transistors
are fabricated using an optimized
version of Agilent’s 10 GHz f
t
, 30
GHz f
max
Self-Aligned-Transistor
(SAT) process. The die are nitride
passivated for surface protection.
Excellent device uniformity,
performance and reliability are
produced by the use of ion-
implantation, self-alignment
techniques, and gold metallization
in the fabrication of these devices.
2
AT-32063 Absolute Maximum Ratings
[1]
Symbol
V
EBO
V
CBO
V
CEO
I
C
P
T
T
j
T
STG
Parameter
Emitter-Base Voltage
Collector-Base Voltage
Collector-Emitter Voltage
Collector Current
Power Dissipation
[2,3]
Junction Temperature
Storage Temperature
Units
V
V
V
mA
mW
°C
°C
Absolute
Maximum
1.5
11
5.5
32
150
150
-65 to 150
Thermal Resistance
[2]
:
θ
jc
= 370°C/W
Notes:
1. Permanent damage may occur if
any of these limits are exceeded.
2. T
Mounting Surface
= 25°C.
3. Derate at 2.7 mW/°C for T
C
> 94.5°C.
4. 150 mW per device.
Electrical Specifications, T
A
= 25°C
Symbol
NF
G
A
h
FE
I
CBO
I
EBO
Parameters and Test Conditions
Noise Figure; V
CE
= 2.7 V, I
C
= 5 mA
Associated Gain; V
CE
= 2.7 V, I
C
= 5 mA
Forward Current Transfer Ratio; V
CE
= 2.7 V, I
C
= 5 mA
Collector Cutoff Current; V
CB
= 3 V
Noise Figure; V
EB
= 1 V
f = 0.9 GHz
f = 0.9 GHz
Units
dB
dB
—
µA
µA
50
Min.
Typ.
1.1
[2]
12.5
[2]
14.5
[2]
270
0.2
1.5
Max.
1.4
[2]
Notes:
1. All data is per individual transistor.
2. Test circuit, Figure 1. Numbers reflect device performance de-embedded from circuit losses. Input loss = 0.2 dB;
output loss = 0.3 dB.
50
Ω
W = 10
L = 450
TEST CIRCUIT
BOARD MATERIAL = 0.047 GETEK (ε = 4.3)
DIMENSIONS IN MILS
NOT TO SCALE
W = 10
L = 100
50
Ω
W = 20
L = 60
Figure 1. Test circuit for Noise Figure and Associated Gain.
This circuit is a compromise match between best noise figure, best gain,
stability, and a practical synthesizable match.
3
AT-32063 Characterization Information, T
A
= 25°C
Symbol
P
1 dB
G
1 dB
IP
3
Parameters and Test Conditions
Power at 1 dB Gain Compression (opt tuning); V
CE
= 2.7 V, I
C
= 20 mA
Gain at 1 dB Gain Compression (opt tuning); V
CE
= 2.7 V, I
C
= 20 mA
Output Third Order Intercept Point (opt tuning); V
CE
= 2.7 V, I
C
= 20 mA
f = 0.9 GHz
f = 0.9 GHz
f = 0.9 GHz
Units
dBm
dB
dBm
Typ.
12
16
24
Typical Performance, T
A
= 25°C
2.00
20.0
15
NOISE FIGURE (dB)
1.50
Ga (dB)
15.0
P1 dB (dBm)
14
13
1.00
10.0
12
0.50
2.7V/2 mA
2.7V/5 mA
2.7V/20 mA
1.8
FREQUENCY (GHz)
2.4
5.0
2.7V/2 mA
2.7V/5 mA
2.7V/20 mA
1.8
FREQUENCY (GHz)
2.4
11
0
0.9
0
0.9
10
0.9
1.8
FREQUENCY (GHz)
2.4
Figure 2. Minimum Noise Figure vs.
Frequency and Current at V
CE
= 2.7 V.
Figure 3. Associated Gain at
Optimum Noise Match vs. Frequency
and Current at V
CE
= 2.7 V.
25
Figure 4. Power at 1 dB Gain
Compression vs. Frequency at
V
CE
= 2.7 V and I
C
= 20 mA.
18
15
12
IP
3
(dBm)
20
G1 dB (dBm)
15
9
6
3
0
0.9
10
2 mA
5 mA
10 mA
20 mA
0
0.5
1.0
1.5
2.0
2.5
5
0
1.8
FREQUENCY (GHz)
2.4
FREQUENCY (GHz)
Figure 5. 1 dB Compressed Gain vs.
Frequency at V
CE
= 2.7 V and
I
C
= 20 mA.
Figure 6. Third Order Intercept vs.
Frequency and Bias at V
CE
= 2.7 V, with
Optimal Tuning.
Real-time operating system RTOS
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